pci_conf_space.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

    	{2'b01, `W_TA2_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ;
    	{2'b01, `W_BA3_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & 
    															 wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1]  = 0 ;
    		r_conf_data_out[0] = wb_ba3_bit0 ;
    	end
    	{2'b01, `W_AM3_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_TA3_ADDR}: 
    	begin
    	    r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_IMG_CTRL4_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ;
    	{2'b01, `W_BA4_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & 
    															 wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1]  = 0 ;
    		r_conf_data_out[0] = wb_ba4_bit0 ;
    	end
    	{2'b01, `W_AM4_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_TA4_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_IMG_CTRL5_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ;
    	{2'b01, `W_BA5_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & 
    															 wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1]  = 0 ;
    		r_conf_data_out[0] = wb_ba5_bit0 ;
    	end
    	{2'b01, `W_AM5_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_TA5_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0]  = 0 ;
    	end
    	{2'b01, `W_ERR_CS_ADDR}: r_conf_data_out = { wb_err_cs_bit31_24, /*13*/14'h0000, /*wb_err_cs_bit10,*/
            									     wb_err_cs_bit9, wb_err_cs_bit8, 7'h00, wb_err_cs_bit0 } ;
    	{2'b01, `W_ERR_ADDR_ADDR}: r_conf_data_out = wb_err_addr ;
    	{2'b01, `W_ERR_DATA_ADDR}: r_conf_data_out = wb_err_data ;

    	{2'b01, `CNF_ADDR_ADDR}: r_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ;
    		// `CNF_DATA_ADDR: implemented elsewhere !!!
    		// `INT_ACK_ADDR : implemented elsewhere !!!
        {2'b01, `ICR_ADDR}: r_conf_data_out = { icr_bit31, 26'h0000_000, icr_bit4_3, icr_bit2_0 } ;
        {2'b01, `ISR_ADDR}: r_conf_data_out = { 27'h0000_000, isr_bit4_3, isr_bit2_0 } ;

    `ifdef PCI_SPOCI
        8'hff: r_conf_data_out = {spoci_cs_nack, 5'h0, spoci_cs_write, spoci_cs_read,
                                  5'h0, spoci_cs_adr[10:8],
                                  spoci_cs_adr[7:0],
                                  spoci_cs_dat[7:0]} ;
    `endif
    	default	: r_conf_data_out = 32'h0000_0000 ;
    	endcase
    end

`endif

`ifdef PCI_SPOCI
reg [ 7: 0] spoci_reg_num ;
wire [11: 0] w_conf_address = init_complete ? w_conf_address_in : {2'b00, spoci_reg_num, 2'b00} ;
`else
wire [11: 0] w_conf_address = w_conf_address_in ;
`endif

always@(w_conf_address or
		status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
		latency_timer or cache_line_size_reg or
		pci_ba0_bit31_12 or
		pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
		pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_12 or pci_ba1_bit0 or
		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_12 or pci_ba2_bit0 or
		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_12 or pci_ba3_bit0 or
		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_12 or pci_ba4_bit0 or
		pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_12 or pci_ba5_bit0 or
		interrupt_line or
		pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or
		pci_err_addr or pci_err_data or
		wb_ba0_bit31_12 or wb_ba0_bit0 or
		wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or
		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or
		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or
		wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or
		wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or
		wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or
		wb_err_addr or wb_err_data or
		cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0

    `ifdef PCI_CPCI_HS_IMPLEMENT
        or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id
    `endif

    `ifdef PCI_SPOCI
        or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat
    `endif
		)
begin
	case (w_conf_address[9:2])
	8'h0:
	begin
		w_conf_data_out = { r_device_id, r_vendor_id } ;
		w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
	end
	8'h1: // w_reg_select_dec bit 0
	begin
		w_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4, 
	 					    4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
		w_reg_select_dec = 57'h000_0000_0000_0001 ;
	end
	8'h2:
	begin
		w_conf_data_out = { r_class_code, r_revision_id } ;
		w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
	end
	8'h3: // w_reg_select_dec bit 1
	begin
		w_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
		w_reg_select_dec = 57'h000_0000_0000_0002 ;
	end
	8'h4: // w_reg_select_dec bit 4
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
		w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address
	end
	8'h5: // w_reg_select_dec bit 8
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
		w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address
	end
	8'h6: // w_reg_select_dec bit 12
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
		w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address
	end
	8'h7: // w_reg_select_dec bit 16
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
		w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address
	end
	8'h8: // w_reg_select_dec bit 20
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
		w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address
	end
	8'h9: // w_reg_select_dec bit 24
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
		w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address
	end
`ifdef PCI_CPCI_HS_IMPLEMENT
    8'hD:
    begin
        w_conf_data_out  = {24'h0000_00, `PCI_CAP_PTR_VAL} ;
        w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register
    end
`endif
	8'hf: // w_reg_select_dec bit 2
	begin
		w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
		w_reg_select_dec = 57'h000_0000_0000_0004 ;
	end
`ifdef PCI_CPCI_HS_IMPLEMENT
    (`PCI_CAP_PTR_VAL >> 2):
    begin
        w_reg_select_dec = 57'h100_0000_0000_0000 ;
        w_conf_data_out  = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ;
    end
`endif
	{2'b01, `P_IMG_CTRL0_ADDR}:  // w_reg_select_dec bit 3
	begin
		w_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
		w_reg_select_dec = 57'h000_0000_0000_0008 ;
	end
    {2'b01, `P_BA0_ADDR}:   // w_reg_select_dec bit 4
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
		w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address
	end
    {2'b01, `P_AM0_ADDR}:   // w_reg_select_dec bit 5
	begin
        w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
		w_reg_select_dec = 57'h000_0000_0000_0020 ;
	end
    {2'b01, `P_TA0_ADDR}:   // w_reg_select_dec bit 6
	begin
        w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
        w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
		w_reg_select_dec = 57'h000_0000_0000_0040 ;
	end
    {2'b01, `P_IMG_CTRL1_ADDR}:   // w_reg_select_dec bit 7
	begin
	    w_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
		w_reg_select_dec = 57'h000_0000_0000_0080 ;
	end
    {2'b01, `P_BA1_ADDR}:   // w_reg_select_dec bit 8
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    	w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    	w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
		w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address
	end
    {2'b01, `P_AM1_ADDR}:   // w_reg_select_dec bit 9
	begin
        w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
        w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
		w_reg_select_dec = 57'h000_0000_0000_0200 ;
	end
    {2'b01, `P_TA1_ADDR}:   // w_reg_select_dec bit 10
	begin
        w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
        w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
		w_reg_select_dec = 57'h000_0000_0000_0400 ;
	end
    {2'b01, `P_IMG_CTRL2_ADDR}:   // w_reg_select_dec bit 11
	begin
	    w_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
		w_reg_select_dec = 57'h000_0000_0000_0800 ;
	end
    {2'b01, `P_BA2_ADDR}:   // w_reg_select_dec bit 12
	begin
    	w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    														  pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;