wb_slave.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

module WB_Slave(
	// Clock and reset
	wb_clk_i, wb_rst_i,
	// WISHBONE Slave I/F
	wbs_cyc_i, wbs_stb_i, wbs_sel_i, wbs_we_i,
	wbs_adr_i, wbs_dat_i, wbs_cti_i,wbs_bte_i,
	wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,

	//dma control out
	dma_base_addr_o,
	dma_length_o,
	dma_rw_o,
	dma_start_o,
	dma_state_i
);
 
// Clock and reset
//
input			wb_clk_i;	// Wishbone Clock
input			wb_rst_i;	// Reset
//
// WISHBONE Slave I/F
//
input			wbs_cyc_i;
input			wbs_stb_i;
input	[3:0]	wbs_sel_i;
input			wbs_we_i;
input	[31:0]	wbs_adr_i;
input	[31:0]	wbs_dat_i;
input			wbs_cti_i,wbs_bte_i;
output	[31:0]	wbs_dat_o;
output			wbs_ack_o;
output			wbs_err_o;
output			wbs_rty_o;

//dma control out
output	[31:0] dma_base_addr_o;
output	[15:0] dma_length_o;
output	dma_rw_o;
output	dma_start_o;
input	[31:0] dma_state_i;

////////////////////////////////////////////Wishbone Slave////////////////////////////////////////

reg			wbs_ack_o;
reg			wbs_rty_o;
reg			wbs_err_o;
reg [31:0]  wbs_dat_o;

reg [31:0] dma_base_addr_o;
reg	[15:0] dma_length_o;
reg	dma_rw_o;
reg	dma_start_o;


always @(posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		wbs_ack_o <=  1'b0;
		wbs_rty_o <=  1'b0;
		wbs_err_o <=  1'b0;
	end else if (wbs_cyc_i & wbs_stb_i) begin
		wbs_ack_o <=  1'b1;
		wbs_rty_o <=  1'b0;
		wbs_err_o <=  1'b0;	
	end else begin
		wbs_ack_o <=  1'b0;
		wbs_rty_o <=  1'b0;
		wbs_err_o <=  1'b0;
	end
end
	
///***********write************//
always @(posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		dma_base_addr_o <= 32'h0;	
		dma_length_o <= 16'h0;
		dma_rw_o <= 1'b0;	
		dma_start_o  <= 1'b0;
	end else begin
		if (wbs_cyc_i && wbs_we_i && wbs_adr_i[11:4] == 8'hff) begin
			case (wbs_adr_i[3:2])
			2'b00:
				dma_base_addr_o <= wbs_dat_i;
			2'b01:
				dma_length_o <= wbs_dat_i[15:0];
			2'b10:
				dma_rw_o <= wbs_dat_i[0];
			2'b11: 
				dma_start_o <= wbs_dat_i[0];
			endcase
		end
	end
end

///********read ************

always@(wbs_adr_i) begin
	if (wbs_adr_i[11:4] == 8'hff) begin
		case (wbs_adr_i[3:2])
			2'b00:   wbs_dat_o = dma_base_addr_o;        
			2'b01:   wbs_dat_o = {16'h0,dma_length_o};
			2'b10:   wbs_dat_o = {30'h0,dma_rw_o};       
			2'b11:   wbs_dat_o = dma_state_i;	 		  
		endcase
	end else begin
		wbs_dat_o = 32'bz;
	end
end

//**********************************************


endmodule