wbs_uart.srd

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

f "noname"; #file 0
f "d:\program files\synplicity\synplify_73\bin\..\lib\xilinx\unisim.v"; #file 1
f "e:\iseprog\pcibridgeguest_uart\uart_wb.v"; #file 2
f "e:\iseprog\pcibridgeguest_uart\uart_defines.v"; #file 3
f "e:\iseprog\pcibridgeguest_uart\raminfr.v"; #file 4
f "e:\iseprog\pcibridgeguest_uart\uart_tfifo.v"; #file 5
f "e:\iseprog\pcibridgeguest_uart\uart_transmitter.v"; #file 6
f "e:\iseprog\pcibridgeguest_uart\uart_rfifo.v"; #file 7
f "e:\iseprog\pcibridgeguest_uart\uart_receiver.v"; #file 8
f "e:\iseprog\pcibridgeguest_uart\uart_regs.v"; #file 9
f "e:\iseprog\pcibridgeguest_uart\uart_debug_if.v"; #file 10
f "e:\iseprog\pcibridgeguest_uart\uart_top.v"; #file 11
f "e:\iseprog\pcibridgeguest_uart\wbs_uart.v"; #file 12
VNAME 'work.uart_wb.verilog'; # view id 0
VNAME 'work.raminfr_4_8_16.verilog'; # view id 1
VNAME 'work.uart_rfifo_11_16_4_5.verilog'; # view id 2
VNAME 'work.uart_tfifo.verilog'; # view id 3
VNAME 'work.uart_transmitter.verilog'; # view id 4
VNAME 'work.uart_receiver.verilog'; # view id 5
VNAME 'work.uart_regs.verilog'; # view id 6
VNAME 'work.uart_debug_if.verilog'; # view id 7
VNAME 'work.uart_top.verilog'; # view id 8
VNAME 'work.wbs_uart.verilog'; # view id 9
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