pci_wb_slave.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

input   [31:0]  SDATA_I ;   // WISHBONE slave interface input data bus
output  [31:0]  SDATA_O ;   // WISHBONE slave interface output data bus
output          ACK_O ;     // Acknowledge output - qualifies valid data on data output bus or received data on data input bus
output          RTY_O ;     // retry output - signals to WISHBONE master that cycle should be terminated and retried later
output          ERR_O ;     // Signals to WISHBONE master that access resulted in an error
input           CAB_I ;     // consecutive address burst input - indicates that master will do a serial address transfer in current cycle

`ifdef REGISTER_WBS_OUTPUTS
reg [31:0]  SDATA_O ;
reg         ACK_O   ;
reg         RTY_O   ;
reg         ERR_O   ;

reg [3:0] del_bc_out ; // delayed transaction bus command output
reg       del_req_out ; // output for issuing delayed transaction requests
reg       del_done_out ; // output indicating current delayed completion finished on WISHBONE bus
reg       del_burst_out ; // delayed burst transaction indicator
reg       del_in_progress_out ; // delayed in progress indicator - since delayed transaction can be a burst transaction, progress indicator must be used for proper operation
reg       del_write_out ;   // write enable for delayed transaction - used for indicating that transaction is a write

`ifdef HOST
reg          wb_conf_wenable_out ;
reg [31:0]   wb_conf_data_out ;    // configuration data output for configuration space
`endif

reg [3:0]  wb_conf_be_out ;      // byte enable outputs for configuration space
reg [31:0] wb_data_out ;

reg [3:0] wb_cbe_out ;

reg       wbw_fifo_wenable_out ;    // write enable for WBW_FIFO output
reg [3:0] wbw_fifo_control_out ;    // control bus output for WBW_FIFO

reg       wbr_fifo_renable_out ;      // WBR_FIFO read enable output
`endif

reg [(`FSM_BITS - 1):0]  c_state ; //current state register

reg [(`FSM_BITS - 1):0]  n_state ; //next state input to current state register

// state machine register control
always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        c_state <= #`FF_DELAY S_IDLE ;
    else
        c_state <= #`FF_DELAY n_state ;
end


// variable for bus command multiplexer logic output for delayed requests
reg [3:0] del_bc ;

//register for intermediate data and select storage
reg [35:0] d_incoming ;

// enable for incoming data register
reg d_incoming_ena ;

// incoming data register control logic
always@(posedge wb_clock_in or posedge reset_in)
begin
    if (reset_in)
        d_incoming <= #`FF_DELAY {35{1'b0}} ;
    else if (d_incoming_ena)
        d_incoming <= #`FF_DELAY {SEL_I, SDATA_I} ;
end

/*===================================================================================================================================================================================
Write allow for image accesses. Writes through images are allowed when all of following are true:
- WBW_FIFO musn't be almost full nor full for image writes to be allowed - Every transaction takes at least two locations in the FIFO
- delayed read from from WISHBONE to PCI request musn't be present
- delayed read from PCI to WISHBONE completion musn't be present
- lock input musn't be set - it can be set because of error reporting or because PCI master state machine is disabled
===================================================================================================================================================================================*/
wire wimg_wallow           = ~|{ wbw_fifo_almost_full_in , wbw_fifo_full_in, wb_del_req_pending_in, pci_drcomp_pending_in, wbs_lock_in } ;
reg img_wallow ;
/*===================================================================================================================================================================================
WISHBONE slave can request an image read accesses when all of following are true:
- delayed completion is not present
- delayed request is not present
- operation is not locked because of error reporting mechanism or because PCI master is disabled
===================================================================================================================================================================================*/
wire wdo_del_request     = ~|{ wb_del_req_pending_in, wb_del_comp_pending_in, wbs_lock_in } ;
reg do_del_request ;
/*===================================================================================================================================================================================
WISHBONE slave can complete an image read accesses when all of following are true:
- delayed read completion is present
- delayed read completion is the same as current read access ( dread_completion_hit is 1 )
- PCI Write FIFO is empty - no posted write is waiting to be finished in PCIW_FIFO
- WBR_FIFO empty status is not active
===================================================================================================================================================================================*/
wire wdel_addr_hit = ( wb_del_addr_in == wb_addr_in ) && ( SEL_I == wb_del_be_in ) ;
reg  del_addr_hit ;
wire wdel_completion_allow = wb_del_comp_pending_in && ((~del_write_in && ~WE_I && pciw_fifo_empty_in && ~wbr_fifo_empty_in) || (del_write_in && WE_I)) ;
reg del_completion_allow ;

/*----------------------------------------------------------------------------------------------------------------------
img_hit - state of wb_hit_in bus when when state machine signals decode is over
---------------------------------------------------------------------------------------------------------------------*/
reg [4:0] img_hit ;
wire wb_hit = |( img_hit ) ;

/*----------------------------------------------------------------------------------------------------------------------
Control logic for image control signals
pref_en - prefetch enable of currently selected image
mrl_en  - Memory read line enable of currently selected image
map     - Address space mapping for currently selected image
---------------------------------------------------------------------------------------------------------------------*/
reg pref_en, mrl_en, map ;
wire wpref_en   = |(wb_pref_en_in & wb_hit_in) ;
wire wmrl_en    = |(wb_mrl_en_in & wb_hit_in) ;
wire wmap       = |(wb_map_in & wb_hit_in) ;

// state machine controls when results from decoders, comparison etc. are sampled into registers to decode an access
reg decode_en ;

reg wb_conf_hit ;
always@(posedge reset_in or posedge wb_clock_in)
begin
    if (reset_in)
    begin
        img_wallow           <= #`FF_DELAY 1'b0 ;
        wb_conf_hit          <= #`FF_DELAY 1'b0 ;
        do_del_request       <= #`FF_DELAY 1'b0 ;
        del_addr_hit         <= #`FF_DELAY 1'b0 ;
        del_completion_allow <= #`FF_DELAY 1'b0 ;
        img_hit              <= #`FF_DELAY 5'h00 ;
        pref_en              <= #`FF_DELAY 1'b0 ;
        mrl_en               <= #`FF_DELAY 1'b0 ;
        map                  <= #`FF_DELAY 1'b0 ;
    end
    else
    if (decode_en)
    begin
        img_wallow           <= #`FF_DELAY wimg_wallow ;
        wb_conf_hit          <= #`FF_DELAY wb_conf_hit_in ;
        do_del_request       <= #`FF_DELAY wdo_del_request ;
        del_addr_hit         <= #`FF_DELAY wdel_addr_hit ;
        del_completion_allow <= #`FF_DELAY wdel_completion_allow ;
        img_hit              <= #`FF_DELAY wb_hit_in ;
        pref_en              <= #`FF_DELAY wpref_en && cache_line_size_not_zero ;
        mrl_en               <= #`FF_DELAY wmrl_en  && cache_line_size_not_zero ;
        map                  <= #`FF_DELAY wmap ;
    end
end

wire   del_burst = CAB_I && (pref_en || mrl_en) && ~WE_I && cache_line_size_not_zero ; // delayed burst indicator - only when WB master attempts CAB transfer and cache line size register is set appropriately and
                                                                                       // either prefetch enable or memory read line enable of corresponding image are set -
                                                                                       // applies for reads only - delayed write cannot be a burst
wire do_dread_completion = del_completion_allow && del_addr_hit ;

`ifdef GUEST

    // wires indicating allowance for configuration cycle generation requests
    wire do_ccyc_req  = 1'b0 ;
    wire do_ccyc_comp = 1'b0 ;

    // wires indicating allowance for interrupt acknowledge cycle generation requests
    wire do_iack_req  = 1'b0 ;
    wire do_iack_comp = 1'b0 ;

    // variables for configuration access control signals
    reg conf_wenable ;
    assign wb_conf_wenable_out = 1'b0 ;

    // configuration cycle data register hit
    wire ccyc_hit = 1'b0 ;
    wire iack_hit = 1'b0 ;

    wire wccyc_hit = 1'b0 ;
    wire wiack_hit = 1'b0 ;

`else
`ifdef HOST
    // only host implementation has access for generating interrupt acknowledge and configuration cycles
    // configuration cycle data register hit
    reg current_delayed_is_ccyc ;
    reg current_delayed_is_iack ;

    wire wccyc_hit = (wb_addr_in[8:2] == {1'b1, `CNF_DATA_ADDR}) ;

    wire wiack_hit = (wb_addr_in[8:2] == {1'b1, `INT_ACK_ADDR})  ;

    reg iack_hit ;
    reg ccyc_hit ;
    always@(posedge reset_in or posedge wb_clock_in)
    begin
        if (reset_in)
        begin
            ccyc_hit <= #`FF_DELAY 1'b0 ;
            iack_hit <= #`FF_DELAY 1'b0 ;
        end
        else
        if (decode_en)
        begin
            ccyc_hit <= #`FF_DELAY wccyc_hit ;
            iack_hit <= #`FF_DELAY wiack_hit ;
        end
    end

    // wires indicating allowance for configuration cycle generation requests
    wire do_ccyc_req  = do_del_request && ccyc_hit;
    wire do_ccyc_comp = del_completion_allow && ccyc_hit && current_delayed_is_ccyc ; // && del_bc_hit

    // wires indicating allowance for interrupt acknowledge cycle generation requests
    wire do_iack_req  = do_del_request && iack_hit ;
    wire do_iack_comp = del_completion_allow && iack_hit && current_delayed_is_iack ; // && del_bc_hit

    // variables for configuration access control signals
    reg conf_wenable ;

    // following flip-flops remember whether current delayed transaction is interrupt acknowledge or configuration cycle transaction
    always@(posedge wb_clock_in or posedge reset_in)
    begin
        if ( reset_in )
        begin
            current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ;
            current_delayed_is_iack <= #`FF_DELAY 1'b0 ;
        end
        else
        if ( del_done_out )
        begin
            current_delayed_is_ccyc <= #`FF_DELAY 1'b0 ;
            current_delayed_is_iack <= #`FF_DELAY 1'b0 ;
        end
        else
        if ( del_req_out && wb_conf_hit )
        begin
            current_delayed_is_ccyc <= #`FF_DELAY do_ccyc_req ;
            current_delayed_is_iack <= #`FF_DELAY do_iack_req ;
        end
    end

`endif
`endif

// configuration read enable - supplied for host and guest bridges
reg conf_renable ;
assign wb_conf_renable_out = conf_renable ;

// burst access indicator
wire burst_transfer = CYC_I && CAB_I ;

// WBW_FIFO control output
reg [3:0] wbw_fifo_control ;

// WBW_FIFO wenable output assignment
reg wbw_fifo_wenable ;

// WBR_FIFO control outputs
reg wbr_fifo_flush, wbr_fifo_renable ; // flush and read enable outputs

// flush signal for WBR_FIFO must be registered, since it asinchronously resets some status registers
wire		wbr_fifo_flush_reg ;
pci_async_reset_flop async_reset_as_wbr_flush
(
    .data_in        	  (wbr_fifo_flush),
    .clk_in         	  (wb_clock_in),
    .async_reset_data_out (wbr_fifo_flush_reg),
    .reset_in    		  (reset_in)
) ;
assign  wbr_fifo_flush_out = wbr_fifo_flush_reg ;

// delayed transaction request control signals
reg del_req, del_done ;

// WISHBONE handshaking control outputs
reg ack, rty, err ;

`ifdef REGISTER_WBS_OUTPUTS
// wire for write attempt - 1 when external WB master is attempting a write
// wire for read attempt  - 1 when external master is attempting a read
wire wattempt = ( CYC_I && STB_I && WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;
wire rattempt = ( CYC_I && STB_I && ~WE_I ) && (!ACK_O && !ERR_O && !RTY_O) ;

`else
// wire for write attempt - 1 when external WB master is attempting a write
// wire for read attempt  - 1 when external master is attempting a read
wire wattempt = ( CYC_I && STB_I && WE_I ) ; // write is qualified when cycle, strobe and write enable inputs are all high
wire rattempt = ( CYC_I && STB_I && ~WE_I ) ; // read is qualified when cycle and strobe are high and write enable is low

`endif
/*----------------------------------------------------------------------------------------------------------------------
Delayed transaction bus command generation
Bus command for delayed reads depends on image's address space mapping and control bits and
whether or not these are interrupt acknowledge requests or configuration cycle requests