ping4.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

/***********************************************************************

  File:   ping.v
  Rev:    3.0.0

  This is an example user application for use with the Xilinx PCI
  initiator.  The design has been tested with the Synopsys design
  flow.

  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.

***********************************************************************/


module ping32 (
                FRAMEQ_N,
                TRDYQ_N,
                IRDYQ_N,
                STOPQ_N,
                DEVSELQ_N,
                ADDR,
                ADIO,
                CFG_VLD,
                CFG_HIT,
                C_TERM,
                C_READY,
                ADDR_VLD,
                BASE_HIT,
                S_TERM,
                S_READY,
                S_ABORT,
                S_WRDN,
                S_SRC_EN,
                S_DATA_VLD,
                S_CBE,
                PCI_CMD,
                REQUEST,
                REQUESTHOLD,
                COMPLETE,
                M_WRDN,
                M_READY,
                M_SRC_EN,
                M_DATA_VLD,
                M_CBE,
                TIME_OUT,
                CFG_SELF,
                M_DATA,
                DR_BUS,
                I_IDLE,
                M_ADDR_N,
                IDLE,
                B_BUSY,
                S_DATA,
                BACKOFF,
                INTR_N,
                PERRQ_N,
                SERRQ_N,
                KEEPOUT,
                CSR,
                SUB_DATA,
                CFG,
                RST,
                CLK,
                PING_DONE,
                PING_REQUEST32
                );
                // synthesis syn_edif_bit_format = "%u<%i>"
                // synthesis syn_edif_scalar_format = "%u"
                // synthesis syn_noclockbuf = 1
                // synthesis syn_hier = "hard"


  // Declare the port directions.

  input         FRAMEQ_N;
  input         TRDYQ_N;
  input         IRDYQ_N;
  input         STOPQ_N;
  input         DEVSELQ_N;
  input  [31:0] ADDR;
  inout  [31:0] ADIO;
  input         CFG_VLD;
  input         CFG_HIT;
  output        C_TERM;
  output        C_READY;
  input         ADDR_VLD;
  input   [7:0] BASE_HIT;
  output        S_TERM;
  output        S_READY;
  output        S_ABORT;
  input         S_WRDN;
  input         S_SRC_EN;
  input         S_DATA_VLD;
  input   [3:0] S_CBE;
  input  [15:0] PCI_CMD;
  output        REQUEST;
  output        REQUESTHOLD;
  output        COMPLETE;
  output        M_WRDN;
  output        M_READY;
  input         M_SRC_EN;
  input         M_DATA_VLD;
  output  [3:0] M_CBE;
  input         TIME_OUT;
  output        CFG_SELF;
  input         M_DATA;
  input         DR_BUS;
  input         I_IDLE;
  input         M_ADDR_N;
  input         IDLE;
  input         B_BUSY;
  input         S_DATA;
  input         BACKOFF;
  output        INTR_N;
  input         PERRQ_N;
  input         SERRQ_N;
  output        KEEPOUT;
  input  [39:0] CSR;
  output [31:0] SUB_DATA;
  input [255:0] CFG;
  input         RST;
  input         CLK;
  output        PING_DONE;
  input         PING_REQUEST32;

  parameter TDLY = 1;


  //******************************************************************//
  // This section contains the PCI interface decode.                  //
  //******************************************************************//

  reg           cfg_rd, bar0_rd, bar1_rd;
  reg           cfg_wr, bar0_wr, bar1_wr;
  wire          cfg_rd_cs, bar0_rd_cs, bar1_rd_cs;
  wire          cfg_wr_cs, bar0_wr_cs, bar1_wr_cs;

  always @(posedge CLK or posedge RST)
  begin : identify
    if (RST)
    begin
      cfg_rd  <= 1'b0;
      cfg_wr  <= 1'b0;
      bar0_rd <= 1'b0;
      bar0_wr <= 1'b0;
      bar1_rd <= 1'b0;
      bar1_wr <= 1'b0;
    end
    else
    begin
      if (CFG_HIT)
      begin
        cfg_rd <= !S_WRDN;
        cfg_wr <= S_WRDN;
      end
      else if (!S_DATA)
      begin
        cfg_rd <= 1'b0;
        cfg_wr <= 1'b0;
      end
      if (BASE_HIT[0])
      begin
        bar0_rd <= !S_WRDN;
        bar0_wr <= S_WRDN;
      end
      else if (!S_DATA)
      begin
        bar0_rd <= 1'b0;
        bar0_wr <= 1'b0;
      end
      if (BASE_HIT[1])
      begin
        bar1_rd <= !S_WRDN;
        bar1_wr <= S_WRDN;
      end
      else if (!S_DATA)
      begin
        bar1_rd <= 1'b0;
        bar1_wr <= 1'b0;
      end
    end
  end

  assign #TDLY cfg_rd_cs  = cfg_rd;
  assign #TDLY cfg_wr_cs  = cfg_wr;
  assign #TDLY bar0_rd_cs = bar0_rd;
  assign #TDLY bar0_wr_cs = bar0_wr;
  assign #TDLY bar1_rd_cs = bar1_rd;
  assign #TDLY bar1_wr_cs = bar1_wr;


  //******************************************************************//
  // This section contains the CFG32 implementation.                  //
  //******************************************************************//

  reg    [31:0] my_cfg_reg;
  wire          oe_cfg_reg;
  wire          en_cfg_reg;

  always @(posedge CLK or posedge RST)
  begin : write_my_cfg_reg
    if (RST) my_cfg_reg <= 32'h00000000;
    else if (S_DATA_VLD & cfg_wr_cs & en_cfg_reg)
    begin
      if (!S_CBE[0]) my_cfg_reg[ 7: 0] <= ADIO[ 7: 0];
      if (!S_CBE[1]) my_cfg_reg[15: 8] <= ADIO[15: 8];
      if (!S_CBE[2]) my_cfg_reg[23:16] <= ADIO[23:16];
      if (!S_CBE[3]) my_cfg_reg[31:24] <= ADIO[31:24];
    end
  end  

  assign #TDLY en_cfg_reg = ADDR[7] | ADDR[6];
  assign #TDLY oe_cfg_reg = en_cfg_reg & cfg_rd_cs & S_DATA & CFG[118];
  assign #TDLY ADIO = oe_cfg_reg ? my_cfg_reg : 32'bz;
  

  //******************************************************************//
  // This section contains the IO32 implementation.                   //
  //******************************************************************//

  reg    [31:0] my_io_reg;
  wire          oe_io_reg;

  always @(posedge CLK or posedge RST)
  begin : write_my_io_reg
    if (RST) my_io_reg <= 32'h10101010;
    else if (S_DATA_VLD & bar0_wr_cs)
    begin
      if (!S_CBE[0]) my_io_reg[ 7: 0] <= ADIO[ 7: 0];
      if (!S_CBE[1]) my_io_reg[15: 8] <= ADIO[15: 8];
      if (!S_CBE[2]) my_io_reg[23:16] <= ADIO[23:16];
      if (!S_CBE[3]) my_io_reg[31:24] <= ADIO[31:24];
    end
  end    

  assign #TDLY oe_io_reg = bar0_rd_cs & S_DATA;
  assign #TDLY ADIO = oe_io_reg ? my_io_reg : 32'bz;


  //******************************************************************//
  // This section contains the MEM32 implementation.                  //
  //******************************************************************//
   
	//final dual port block ram edition!!! 

  wire          oe_mem;       //
  wire          en1,en2,en10,en11,en12,en13;
  wire          wea;		  //write
  wire          web;		  //read
 
  wire   [31:0] dataout;
  wire   [6:0]	 addr;		 //128DWord
 
 
  assign #TDLY oe_mem = bar1_rd_cs & S_DATA;
  assign  ADIO = oe_mem ? dataout : 32'bz;	 //target read!

  assign  en1=S_DATA_VLD & bar1_wr_cs;
  assign  en10=en1&(!S_CBE[0]);
  assign  en11=en1&(!S_CBE[1]);
  assign  en12=en1&(!S_CBE[2]);
  assign  en13=en1&(!S_CBE[3]);
    
  assign  en2=BASE_HIT[1];
  assign  wea=bar1_wr_cs;
  assign  web=1'b0;		    
  assign  addr=ADDR[8:2];
  

  
dpramb dpramb0(
	.addra(addr),
	.addrb(addr),
	.clka(CLK),
	.clkb(CLK),
	.dina(ADIO[7:0]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[7:0]),
	.ena(en10),
	.enb(en2),
	.wea(wea),
	.web(web)
	);


dpramb dpramb1(
	.addra(addr),
	.addrb(addr),
	.clka(CLK),
	.clkb(CLK),
	.dina(ADIO[15:8]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[15:8]),
	.ena(en11),
	.enb(en2),
	.wea(wea),
	.web(web)
	);


dpramb dpramb2(
	.addra(addr),
	.addrb(addr),
	.clka(CLK),
	.clkb(CLK),
	.dina(ADIO[23:16]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[23:16]),
	.ena(en12),
	.enb(en2),
	.wea(wea),
	.web(web)
	);


dpramb dpramb3(
	.addra(addr),
	.addrb(addr),
	.clka(CLK),
	.clkb(CLK),
	.dina(ADIO[31:24]),
//	.dinb(),
//	.douta(),
	.doutb(dataout[31:24]),
	.ena(en13),
	.enb(en2),
	.wea(wea),
	.web(web)
	);
  
  //******************************************************************//
  // This section contains the initiator logic.                       //
  //******************************************************************//

 
  //******************************************************************//
  // This section contains unused signals.                            //
  //******************************************************************//

  assign #TDLY C_TERM = 1'b1;
  assign #TDLY C_READY = 1'b1;
  assign #TDLY KEEPOUT = 1'b0;
  assign #TDLY CFG_SELF = 1'b0;
  assign #TDLY REQUESTHOLD = 1'b0;
  assign #TDLY SUB_DATA = 32'h00000000;

  reg           S_TERM_reg;
  reg           S_READY_reg;
  reg           S_ABORT_reg;
  reg           M_READY_reg;
  reg           INTR_N_reg;
 
  always @(posedge CLK or posedge RST)
  begin : dont_optimize_please
    if (RST)
    begin
      INTR_N_reg <= 1'b0;
      S_TERM_reg <= 1'b1;
      S_READY_reg <= 1'b0;
      S_ABORT_reg <= 1'b1;
      M_READY_reg <= 1'b0;
    end
    else
    begin
      INTR_N_reg <= 1'b1;
      S_TERM_reg <= 1'b0;
      S_READY_reg <= 1'b1;
      S_ABORT_reg <= 1'b0;
      M_READY_reg <= 1'b1;
    end
  end

  assign #TDLY INTR_N = INTR_N_reg;
  assign #TDLY S_TERM = S_TERM_reg;
  assign #TDLY S_READY = S_READY_reg;
  assign #TDLY S_ABORT = S_ABORT_reg;
  assign #TDLY M_READY = M_READY_reg;


endmodule