wb_slave.tlg

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

Selecting top level module WB_Slave
Synthesizing module WB_Slave
@N: CL177 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":54:0:54:5|Sharing sequential element wbs_err_o.
@W: CG296 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":95:8:95:16|Incomplete sensitivity list - assuming completeness
@W: CG290 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":98:24:98:38|Referenced variable dma_base_addr_o is not in sensitivity list
@W: CG290 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":99:31:99:42|Referenced variable dma_length_o is not in sensitivity list
@W: CG290 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":100:31:100:38|Referenced variable dma_rw_o is not in sensitivity list
@W: CG290 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":101:31:101:41|Referenced variable dma_start_o is not in sensitivity list
@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":54:0:54:5|All reachable assignments to wbs_rty_o assign 0, register removed by optimization
@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":25:12:25:20|Input port bit <3> of wbs_sel_i[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":25:12:25:20|Input port bit <2> of wbs_sel_i[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":25:12:25:20|Input port bit <1> of wbs_sel_i[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":25:12:25:20|Input port bit <0> of wbs_sel_i[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <31> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <30> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <29> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <28> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <27> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <26> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <25> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <24> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <23> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <22> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <21> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <20> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <19> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <18> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <17> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <16> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <15> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <14> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <13> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <12> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <1> of wbs_adr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":27:13:27:21|Input port bit <0> of wbs_adr_i[31:0] is unused

@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":25:12:25:20|Input wbs_sel_i is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":29:8:29:16|Input wbs_cti_i is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Slave.v":29:18:29:26|Input wbs_bte_i is unused