pci_bridge.ucf

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

# Place a logic element(called a BEL) in a specific CLB location.
# BEL = FF, LUT, RAM, etc...
# -----------------------
#INST instance_path/BEL_inst_name  LOC = CLB_R17C36
#
# -----------------------
# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7
#
# -----------------------
# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1* LOC=clb_r1c1:clb_r5c7
#
# -----------------------
# Prohibit IO pin P26 or CLBR5C3 from being used:
# -----------------------
#CONFIG PROHIBIT = P26
#CONFIG PROHIBIT = CLB_R5C3
# Config Prohibit is very important for forcing the software to not use critical
# configuration pins like INIT or DOUT on the FPGA.  The Mode pins and JTAG
# Pins require a special pad so they will not be available to this constraint
#
# -----------------------
# Assign an OBUF to be FAST or SLOW:
# -----------------------
#INST obuf_instance_name FAST
#INST obuf_instance_name SLOW
#
# -----------------------
# FPGAs only:  IOB input Flip-flop delay specification
# -----------------------
# Declare an IOB input FF delay (default = MAXDELAY).
# NOTE:  MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
# into an IOB by the "map -pr i" option.
#INST input_ff_instance_name MEDDELAY
#INST input_ff_instance_name NODELAY
#
# -----------------------
# Assign Global Clock Buffers Lower Left Right Side
# -----------------------
# INST gbuf1 LOC=SSW
#
# #
NET "CLK" IOSTANDARD = PCI33_5;
NET "CLK" TNM_NET = "CLK";
#NET "CRT_CLK"   TNM_NET = "CRT_CLK"
#TIMESPEC "TS_CLK"       = PERIOD "CLK" 30 ns HIGH 50 %
#TIMESPEC "TS_CRT_CLK"   = PERIOD "CRT_CLK" 44 ns HIGH 50 %
#TIMESPEC "TS_CLK_2_CRT_CLK" = FROM : "CLK"     : TO : "CRT_CLK" : 5
#TIMESPEC "TS_CRT_CLK_2_CLK" = FROM : "CRT_CLK" : TO : "CLK"     : 5
INST "AD0.PAD" TNM = "PCI_AD";
INST "AD1.PAD" TNM = "PCI_AD";
INST "AD2.PAD" TNM = "PCI_AD";
INST "AD3.PAD" TNM = "PCI_AD";
INST "AD4.PAD" TNM = "PCI_AD";
INST "AD5.PAD" TNM = "PCI_AD";
INST "AD6.PAD" TNM = "PCI_AD";
INST "AD7.PAD" TNM = "PCI_AD";
INST "AD8.PAD" TNM = "PCI_AD";
INST "AD9.PAD" TNM = "PCI_AD";
INST "AD10.PAD" TNM = "PCI_AD";
INST "AD11.PAD" TNM = "PCI_AD";
INST "AD12.PAD" TNM = "PCI_AD";
INST "AD13.PAD" TNM = "PCI_AD";
INST "AD14.PAD" TNM = "PCI_AD";
INST "AD15.PAD" TNM = "PCI_AD";
INST "AD16.PAD" TNM = "PCI_AD";
INST "AD17.PAD" TNM = "PCI_AD";
INST "AD18.PAD" TNM = "PCI_AD";
INST "AD19.PAD" TNM = "PCI_AD";
INST "AD20.PAD" TNM = "PCI_AD";
INST "AD21.PAD" TNM = "PCI_AD";
INST "AD22.PAD" TNM = "PCI_AD";
INST "AD23.PAD" TNM = "PCI_AD";
INST "AD24.PAD" TNM = "PCI_AD";
INST "AD25.PAD" TNM = "PCI_AD";
INST "AD26.PAD" TNM = "PCI_AD";
INST "AD27.PAD" TNM = "PCI_AD";
INST "AD28.PAD" TNM = "PCI_AD";
INST "AD29.PAD" TNM = "PCI_AD";
INST "AD30.PAD" TNM = "PCI_AD";
INST "AD31.PAD" TNM = "PCI_AD";
TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK"  ;
TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "AD0" IOSTANDARD = PCI33_5;
NET "AD1" IOSTANDARD = PCI33_5;
NET "AD2" IOSTANDARD = PCI33_5;
NET "AD3" IOSTANDARD = PCI33_5;
NET "AD4" IOSTANDARD = PCI33_5;
NET "AD5" IOSTANDARD = PCI33_5;
NET "AD6" IOSTANDARD = PCI33_5;
NET "AD7" IOSTANDARD = PCI33_5;
NET "AD8" IOSTANDARD = PCI33_5;
NET "AD9" IOSTANDARD = PCI33_5;
NET "AD10" IOSTANDARD = PCI33_5;
NET "AD11" IOSTANDARD = PCI33_5;
NET "AD12" IOSTANDARD = PCI33_5;
NET "AD13" IOSTANDARD = PCI33_5;
NET "AD14" IOSTANDARD = PCI33_5;
NET "AD15" IOSTANDARD = PCI33_5;
NET "AD16" IOSTANDARD = PCI33_5;
NET "AD17" IOSTANDARD = PCI33_5;
NET "AD18" IOSTANDARD = PCI33_5;
NET "AD19" IOSTANDARD = PCI33_5;
NET "AD20" IOSTANDARD = PCI33_5;
NET "AD21" IOSTANDARD = PCI33_5;
NET "AD22" IOSTANDARD = PCI33_5;
NET "AD23" IOSTANDARD = PCI33_5;
NET "AD24" IOSTANDARD = PCI33_5;
NET "AD25" IOSTANDARD = PCI33_5;
NET "AD26" IOSTANDARD = PCI33_5;
NET "AD27" IOSTANDARD = PCI33_5;
NET "AD28" IOSTANDARD = PCI33_5;
NET "AD29" IOSTANDARD = PCI33_5;
NET "AD30" IOSTANDARD = PCI33_5;
NET "AD31" IOSTANDARD = PCI33_5;
INST "CBE0.PAD" TNM = "PCI_CBE";
INST "CBE1.PAD" TNM = "PCI_CBE";
INST "CBE2.PAD" TNM = "PCI_CBE";
INST "CBE3.PAD" TNM = "PCI_CBE";
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK"  ;
TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "CBE0" IOSTANDARD = PCI33_5;
NET "CBE1" IOSTANDARD = PCI33_5;
NET "CBE2" IOSTANDARD = PCI33_5;
NET "CBE3" IOSTANDARD = PCI33_5;
#INST "DEVSEL.PAD" TNM = "PCI_CTRL"
NET "DEVSEL" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "DEVSEL" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "DEVSEL" IOSTANDARD = PCI33_5;
NET "FRAME" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "FRAME" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "FRAME" IOSTANDARD = PCI33_5;
#INST "FRAME.PAD" TNM = "PCI_CTRL"
NET "GNT" OFFSET = IN 10 ns BEFORE "CLK"  ;
NET "GNT" IOSTANDARD = PCI33_5;
NET "RST" IOSTANDARD = PCI33_5;
NET "INTA" IOSTANDARD = PCI33_5;
#INST "GNT.PAD" TNM = "PCI_GNT"
NET "IRDY" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "IRDY" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "IRDY" IOSTANDARD = PCI33_5;
#INST "IRDY.PAD" TNM="PCI_CTRL"
NET "PAR" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "PAR" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "PAR" IOSTANDARD = PCI33_5;
#INST "PAR.PAD" TNM = "PCI_CTRL"
NET "PERR" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "PERR" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "PERR" IOSTANDARD = PCI33_5;
#INST "PERR.PAD" TNM = "PCI_CTRL"
NET "REQ" OFFSET = OUT 12 ns AFTER "CLK"  ;
NET "REQ" IOSTANDARD = PCI33_5;
#INST "REQ.PAD" TNM = "PCI_REQ"
NET "SERR" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "SERR" IOSTANDARD = PCI33_5;
#INST "SERR.PAD" TNM = "PCI_CTRL"
NET "STOP" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "STOP" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "STOP" IOSTANDARD = PCI33_5;
#INST "STOP.PAD" TNM = "PCI_CTRL"
NET "TRDY" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "TRDY" OFFSET = OUT 11 ns AFTER "CLK"  ;
NET "TRDY" IOSTANDARD = PCI33_5;
#INST "TRDY.PAD" TNM = "PCI_CTRL"
NET "IDSEL" OFFSET = IN 7 ns BEFORE "CLK"  ;
NET "IDSEL" IOSTANDARD = PCI33_5;
##################################################################################
# Pin locations
##################################################################################
#NET "EX_CLK" LOC = "P182";

###################################################################################

NET "CLK" LOC = "P185";
NET "INTA" LOC = "P195";
NET "RST" LOC = "P199";
NET "GNT" LOC = "P200";
NET "REQ" LOC = "P201";
NET "AD31" LOC = "P203";
NET "AD30" LOC = "P204";
NET "AD29" LOC = "P205";
NET "AD28" LOC = "P206";
NET "AD27" LOC = "P3";
NET "AD26" LOC = "P4";
NET "AD25" LOC = "P5";
NET "AD24" LOC = "P6";
NET "CBE3" LOC = "P8";
NET "IDSEL" LOC = "P9";
NET "AD23" LOC = "P10";
NET "AD22" LOC = "P14";
NET "AD21" LOC = "P15";
NET "AD20" LOC = "P16";
NET "AD19" LOC = "P17";
NET "AD18" LOC = "P18";
NET "AD17" LOC = "P20";
NET "AD16" LOC = "P21";
NET "CBE2" LOC = "P22";
NET "FRAME" LOC = "P23";
NET "IRDY" LOC = "P24";
#
NET "TRDY" LOC = "P27";
NET "DEVSEL" LOC = "P29";
NET "STOP" LOC = "P30";
NET "PERR" LOC = "P31";
NET "SERR" LOC = "P33";
NET "PAR" LOC = "P34";
NET "CBE1" LOC = "P35";
NET "AD15" LOC = "P36";
NET "AD14" LOC = "P37";
NET "AD13" LOC = "P41";
NET "AD12" LOC = "P42";
NET "AD11" LOC = "P43";
NET "AD10" LOC = "P45";
NET "AD9" LOC = "P46";
NET "AD8" LOC = "P47";
NET "CBE0" LOC = "P48";
NET "AD7" LOC = "P49";
NET "AD6" LOC = "P57";
NET "AD5" LOC = "P58";
NET "AD4" LOC = "P59";
NET "AD3" LOC = "P61";
NET "AD2" LOC = "P62";
NET "AD1" LOC = "P63";
NET "AD0" LOC = "P67";
#
#NET  "HSYNC"							LOC = "P188"
#NET  "VSYNC"							LOC = "P187"
#NET  "RGB<0>"							LOC = "P81"
#NET  "RGB<1>"							LOC = "P82"
#NET  "RGB<2>"							LOC = "P83"
#NET  "RGB<3>"							LOC = "P84"
#
#
##################################################################################
# IOB force
##################################################################################
#INST "bridge/wishbone_slave_unit/pci_initiator_if" TNM=FFS:PCI_MIF_FFS
#INST "bridge/wishbone_slave_unit/pci_initiator_sm" TNM=FFS:PCI_MSM_FFS
#INST "bridge/pci_io_mux/frame_iob/dat_out_reg" TNM=FFS:PCI_O_FFS
#INST "bridge/parity_checker" TNM=FFS:PCI_PAR_FFS
#INST "bridge/input_register" TNM=FFS:PCI_I_FFS
#TIMEGRP "ALL_PCI_FFS" = "PCI_O_FFS"
#TIMESPEC TS_PCI_AD_SETUP   = FROM : "PCI_AD"   : TO : "ALL_PCI_FFS" :  7.000
#TIMESPEC TS_PCI_CBE_SETUP  = FROM : "PCI_CBE"  : TO : "ALL_PCI_FFS" :  7.000
#TIMESPEC TS_PCI_CTRL_SETUP = FROM : "PCI_CTRL" : TO : "ALL_PCI_FFS" :  7.000
#TIMESPEC TS_PCI_REQ_TIME_OUT    = FROM : "ALL_PCI_FFS" : TO : "PCI_REQ" :  12.000
#TIMESPEC TS_PCI_GNT_SETUP       = FROM : "PCI_GNT"     : TO : "ALL_PCI_FFS" :  10.000
#TIMESPEC TS_PCI_AD_HOLD   = FROM : "ALL_PCI_FFS"   : TO : "PCI_AD" :  11.000
#TIMESPEC TS_PCI_CBE_HOLD  = FROM : "ALL_PCI_FFS"  : TO : "PCI_CBE" :  11.000
#TIMESPEC TS_PCI_CTRL_HOLD = FROM : "ALL_PCI_FFS" : TO : "PCI_CTRL" :  11.000
#NET "EX_CLK" TNM_NET = "EX_CLK";
#TIMESPEC "TS_EX_CLK" = PERIOD "EX_CLK" 20 ns HIGH 50 %;