pci_wb_slave_unit.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

    .wbr_renable_in            (fifos_wbr_renable_in),
    .wbr_data_out              (fifos_wbr_data_out),
    .wbr_be_out                (fifos_wbr_be_out),
    .wbr_control_out           (fifos_wbr_control_out),
    .wbr_flush_in              (fifos_wbr_flush_in),
    .wbr_empty_out             (fifos_wbr_empty_out)

`ifdef PCI_BIST
    ,
    .mbist_si_i       (mbist_si_i),
    .mbist_so_o       (mbist_so_o),
    .mbist_ctrl_i       (mbist_ctrl_i)
`endif
) ;

wire [31:0] amux_addr_in  = ADDR_I ;
wire        amux_sample_address_in = wbs_sm_sample_address_out ;

wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar0_in   =   wbu_bar0_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar1_in   =   wbu_bar1_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar2_in   =   wbu_bar2_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar3_in   =   wbu_bar3_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar4_in   =   wbu_bar4_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar5_in   =   wbu_bar5_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am0_in    =   wbu_am0_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am1_in    =   wbu_am1_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am2_in    =   wbu_am2_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am3_in    =   wbu_am3_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am4_in    =   wbu_am4_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am5_in    =   wbu_am5_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta0_in    =   wbu_ta0_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta1_in    =   wbu_ta1_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta2_in    =   wbu_ta2_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta3_in    =   wbu_ta3_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta4_in    =   wbu_ta4_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta5_in    =   wbu_ta5_in ;
wire [5:0]  amux_at_en_in = wbu_at_en_in ;

pci_wb_addr_mux wb_addr_dec
(
    `ifdef REGISTER_WBS_OUTPUTS
    .clk_in      (wb_clock_in),
    .reset_in    (reset_in),
    .sample_address_in (amux_sample_address_in),
    `endif
    .address_in  (amux_addr_in),
    .bar0_in     (amux_bar0_in),
    .bar1_in     (amux_bar1_in),
    .bar2_in     (amux_bar2_in),
    .bar3_in     (amux_bar3_in),
    .bar4_in     (amux_bar4_in),
    .bar5_in     (amux_bar5_in),
    .am0_in      (amux_am0_in),
    .am1_in      (amux_am1_in),
    .am2_in      (amux_am2_in),
    .am3_in      (amux_am3_in),
    .am4_in      (amux_am4_in),
    .am5_in      (amux_am5_in),
    .ta0_in      (amux_ta0_in),
    .ta1_in      (amux_ta1_in),
    .ta2_in      (amux_ta2_in),
    .ta3_in      (amux_ta3_in),
    .ta4_in      (amux_ta4_in),
    .ta5_in      (amux_ta5_in),
    .at_en_in    (amux_at_en_in),
    .hit_out     (amux_hit_out),
    .address_out (amux_address_out)
);

// delayed transaction logic inputs
wire        del_sync_req_in             =       wbs_sm_del_req_out ;
wire        del_sync_comp_in            =       pcim_if_del_complete_out ;
wire        del_sync_done_in            =       wbs_sm_del_done_out ;
wire        del_sync_in_progress_in     =       wbs_sm_del_in_progress_out ;
wire [31:0] del_sync_addr_in            =       wbs_sm_data_out ;
wire [3:0]  del_sync_be_in              =       wbs_sm_conf_be_out ;
wire        del_sync_we_in              =       wbs_sm_del_write_out ;
wire [3:0]  del_sync_bc_in              =       wbs_sm_del_bc_out ;
wire        del_sync_status_in          =       pcim_if_del_error_out ;
wire        del_sync_burst_in           =       wbs_sm_del_burst_out ;
wire        del_sync_retry_expired_in   =       pcim_if_del_rty_exp_out ;

// delayed transaction logic instantiation
pci_delayed_sync del_sync  (
                            .reset_in             (reset_in),
                            .req_clk_in           (wb_clock_in),
                            .comp_clk_in          (pci_clock_in),
                            .req_in               (del_sync_req_in),
                            .comp_in              (del_sync_comp_in),
                            .done_in              (del_sync_done_in),
                            .in_progress_in       (del_sync_in_progress_in),
                            .comp_req_pending_out (del_sync_comp_req_pending_out),
                            .comp_comp_pending_out(del_sync_comp_comp_pending_out),
                            .req_req_pending_out  (del_sync_req_req_pending_out),
                            .req_comp_pending_out (del_sync_req_comp_pending_out),
                            .addr_in              (del_sync_addr_in),
                            .be_in                (del_sync_be_in),
                            .addr_out             (del_sync_addr_out),
                            .be_out               (del_sync_be_out),
                            .we_in                (del_sync_we_in),
                            .we_out               (del_sync_we_out),
                            .bc_in                (del_sync_bc_in),
                            .bc_out               (del_sync_bc_out),
                            .status_in            (del_sync_status_in),
                            .status_out           (del_sync_status_out),
                            .comp_flush_out       (del_sync_comp_flush_out),
                            .burst_in             (del_sync_burst_in),
                            .burst_out            (del_sync_burst_out),
                            .retry_expired_in     (del_sync_retry_expired_in)
                        );

// delayed write storage inputs
wire        del_write_we_in         =       wbs_sm_del_req_out && wbs_sm_del_write_out ;
wire [31:0] del_write_data_in       =       wbs_sm_conf_data_out ;

pci_delayed_write_reg delayed_write_data
(
	.reset_in       (reset_in),
	.req_clk_in     (wb_clock_in),
	.comp_wdata_out (del_write_data_out),
	.req_we_in      (del_write_we_in),
	.req_wdata_in   (del_write_data_in)
);

`ifdef HOST
    // configuration cycle address decoder input
    wire    [31:0]      ccyc_addr_in = {8'h00, wbu_ccyc_addr_in} ;

    pci_conf_cyc_addr_dec ccyc_addr_dec
    (
        .ccyc_addr_in   (ccyc_addr_in),
        .ccyc_addr_out  (ccyc_addr_out)
    ) ;
`else
`ifdef GUEST
    assign ccyc_addr_out = 32'h0000_0000 ;
`endif
`endif

// pci master interface inputs
wire [31:0] pcim_if_wbw_addr_data_in            =           fifos_wbw_addr_data_out ;
wire [3:0]  pcim_if_wbw_cbe_in                  =           fifos_wbw_cbe_out ;
wire [3:0]  pcim_if_wbw_control_in              =           fifos_wbw_control_out ;
wire        pcim_if_wbw_empty_in                =           fifos_wbw_empty_out ;
wire        pcim_if_wbw_transaction_ready_in    =           fifos_wbw_transaction_ready_out ;
wire [31:0] pcim_if_data_in                     =           pcim_sm_data_out ;
wire [31:0] pcim_if_del_wdata_in                =           del_write_data_out ;
wire        pcim_if_del_req_in                  =           del_sync_comp_req_pending_out ;
wire [31:0] pcim_if_del_addr_in                 =           del_sync_addr_out ;
wire [3:0]  pcim_if_del_bc_in                   =           del_sync_bc_out ;
wire [3:0]  pcim_if_del_be_in                   =           del_sync_be_out ;
wire        pcim_if_del_burst_in                =           del_sync_burst_out ;
wire        pcim_if_del_we_in                   =           del_sync_we_out ;
wire [7:0]  pcim_if_cache_line_size_in          =           wbu_cache_line_size_in ;
wire        pcim_if_wait_in                     =           pcim_sm_wait_out ;
wire        pcim_if_wtransfer_in                =           pcim_sm_wtransfer_out ;
wire        pcim_if_rtransfer_in                =           pcim_sm_rtransfer_out ;
wire        pcim_if_retry_in                    =           pcim_sm_retry_out ;
wire        pcim_if_rerror_in                   =           pcim_sm_rerror_out ;
wire        pcim_if_first_in                    =           pcim_sm_first_out ;
wire        pcim_if_mabort_in                   =           pcim_sm_mabort_out ;

pci_master32_sm_if pci_initiator_if
(
    .clk_in                        (pci_clock_in),
    .reset_in                      (reset_in),
    .address_out                   (pcim_if_address_out),
    .bc_out                        (pcim_if_bc_out),
    .data_out                      (pcim_if_data_out),
    .data_in                       (pcim_if_data_in),
    .be_out                        (pcim_if_be_out),
    .req_out                       (pcim_if_req_out),
    .rdy_out                       (pcim_if_rdy_out),
    .last_out                      (pcim_if_last_out),
    .wbw_renable_out               (pcim_if_wbw_renable_out),
    .wbw_fifo_addr_data_in         (pcim_if_wbw_addr_data_in),
    .wbw_fifo_cbe_in               (pcim_if_wbw_cbe_in),
    .wbw_fifo_control_in           (pcim_if_wbw_control_in),
    .wbw_fifo_empty_in             (pcim_if_wbw_empty_in),
    .wbw_fifo_transaction_ready_in (pcim_if_wbw_transaction_ready_in),
    .wbr_fifo_wenable_out          (pcim_if_wbr_wenable_out),
    .wbr_fifo_data_out             (pcim_if_wbr_data_out),
    .wbr_fifo_be_out               (pcim_if_wbr_be_out),
    .wbr_fifo_control_out          (pcim_if_wbr_control_out),
    .del_wdata_in                  (pcim_if_del_wdata_in),
    .del_complete_out              (pcim_if_del_complete_out),
    .del_req_in                    (pcim_if_del_req_in),
    .del_addr_in                   (pcim_if_del_addr_in),
    .del_bc_in                     (pcim_if_del_bc_in),
    .del_be_in                     (pcim_if_del_be_in),
    .del_burst_in                  (pcim_if_del_burst_in),
    .del_error_out                 (pcim_if_del_error_out),
    .del_rty_exp_out               (pcim_if_del_rty_exp_out),
    .del_we_in                     (pcim_if_del_we_in),
    .err_addr_out                  (pcim_if_err_addr_out),
    .err_bc_out                    (pcim_if_err_bc_out),
    .err_signal_out                (pcim_if_err_signal_out),
    .err_source_out                (pcim_if_err_source_out),
    .err_rty_exp_out               (pcim_if_err_rty_exp_out),
    .cache_line_size_in            (pcim_if_cache_line_size_in),
    .mabort_received_out           (pcim_if_mabort_out),
    .tabort_received_out           (pcim_if_tabort_out),
    .next_data_out                 (pcim_if_next_data_out),
    .next_be_out                   (pcim_if_next_be_out),
    .next_last_out                 (pcim_if_next_last_out),
    .wait_in                       (pcim_if_wait_in),
    .wtransfer_in                  (pcim_if_wtransfer_in),
    .rtransfer_in                  (pcim_if_rtransfer_in),
    .retry_in                      (pcim_if_retry_in),
    .rerror_in                     (pcim_if_rerror_in),
    .first_in                      (pcim_if_first_in),
    .mabort_in                     (pcim_if_mabort_in),
    .posted_write_not_present_out  (pcim_if_posted_write_not_present_out)
);

// pci master state machine inputs
wire        pcim_sm_gnt_in                  =       wbu_pciif_gnt_in ;
wire        pcim_sm_frame_in                =       wbu_pciif_frame_in ;
wire        pcim_sm_irdy_in                 =       wbu_pciif_irdy_in ;
wire        pcim_sm_trdy_in                 =       wbu_pciif_trdy_in;
wire        pcim_sm_stop_in                 =       wbu_pciif_stop_in ;
wire        pcim_sm_devsel_in               =       wbu_pciif_devsel_in ;
wire [31:0] pcim_sm_ad_reg_in               =       wbu_pciif_ad_reg_in ;
wire [31:0] pcim_sm_address_in              =       pcim_if_address_out ;
wire [3:0]  pcim_sm_bc_in                   =       pcim_if_bc_out ;
wire [31:0] pcim_sm_data_in                 =       pcim_if_data_out ;
wire [3:0]  pcim_sm_be_in                   =       pcim_if_be_out ;
wire        pcim_sm_req_in                  =       pcim_if_req_out ;
wire        pcim_sm_rdy_in                  =       pcim_if_rdy_out ;
wire        pcim_sm_last_in                 =       pcim_if_last_out ;
wire [7:0]  pcim_sm_latency_tim_val_in      =       wbu_latency_tim_val_in ;
wire [31:0] pcim_sm_next_data_in            =       pcim_if_next_data_out ;
wire [3:0]  pcim_sm_next_be_in              =       pcim_if_next_be_out ;
wire        pcim_sm_next_last_in            =       pcim_if_next_last_out ;
wire        pcim_sm_trdy_reg_in             =       wbu_pciif_trdy_reg_in ;
wire        pcim_sm_stop_reg_in             =       wbu_pciif_stop_reg_in ;
wire        pcim_sm_devsel_reg_in           =       wbu_pciif_devsel_reg_in ;
wire        pcim_sm_frame_en_in             =       wbu_pciif_frame_en_in ;
wire        pcim_sm_frame_out_in            =       wbu_pciif_frame_out_in ;

pci_master32_sm pci_initiator_sm
(
    .clk_in                     (pci_clock_in),
    .reset_in                   (reset_in),
    .pci_req_out                (pcim_sm_req_out),
    .pci_gnt_in                 (pcim_sm_gnt_in),
    .pci_frame_in               (pcim_sm_frame_in),
    .pci_frame_out              (pcim_sm_frame_out),
    .pci_frame_en_out           (pcim_sm_frame_en_out),
    .pci_frame_out_in           (pcim_sm_frame_out_in),
    .pci_frame_load_out         (pcim_sm_frame_load_out),
    .pci_frame_en_in            (pcim_sm_frame_en_in),
    .pci_irdy_in                (pcim_sm_irdy_in),
    .pci_irdy_out               (pcim_sm_irdy_out),
    .pci_irdy_en_out            (pcim_sm_irdy_en_out),
    .pci_trdy_in                (pcim_sm_trdy_in),
    .pci_trdy_reg_in            (pcim_sm_trdy_reg_in),
    .pci_stop_in                (pcim_sm_stop_in),
    .pci_stop_reg_in            (pcim_sm_stop_reg_in),
    .pci_devsel_in              (pcim_sm_devsel_in),
    .pci_devsel_reg_in          (pcim_sm_devsel_reg_in),
    .pci_ad_reg_in              (pcim_sm_ad_reg_in),
    .pci_ad_out                 (pcim_sm_ad_out),
    .pci_ad_en_out              (pcim_sm_ad_en_out),
    .pci_cbe_out                (pcim_sm_cbe_out),
    .pci_cbe_en_out             (pcim_sm_cbe_en_out),
    .address_in                 (pcim_sm_address_in),
    .bc_in                      (pcim_sm_bc_in),
    .data_in                    (pcim_sm_data_in),
    .data_out                   (pcim_sm_data_out),
    .be_in                      (pcim_sm_be_in),
    .req_in                     (pcim_sm_req_in),
    .rdy_in                     (pcim_sm_rdy_in),
    .last_in                    (pcim_sm_last_in),
    .latency_tim_val_in         (pcim_sm_latency_tim_val_in),
    .next_data_in               (pcim_sm_next_data_in),
    .next_be_in                 (pcim_sm_next_be_in),
    .next_last_in               (pcim_sm_next_last_in),
    .ad_load_out                (pcim_sm_ad_load_out),
    .ad_load_on_transfer_out    (pcim_sm_ad_load_on_transfer_out),
    .wait_out                   (pcim_sm_wait_out),
    .wtransfer_out              (pcim_sm_wtransfer_out),
    .rtransfer_out              (pcim_sm_rtransfer_out),
    .retry_out                  (pcim_sm_retry_out),
    .rerror_out                 (pcim_sm_rerror_out),
    .first_out                  (pcim_sm_first_out),
    .mabort_out                 (pcim_sm_mabort_out)
) ;

endmodule