top.vtc

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

//
// Verplex constraint file
// Generated using Synplify-pro
//
// Copyright (c) 1996-2002 Synplicity, Inc.
// All rights reserved
//

// Set parsing options
set log file TOP.vlf -replace
set naming rule "%s_Z" -register -golden
set naming rule "%s" -register -revised
set case sensitivity off
// set undriven signal 0 -both
// set undefined cell black_box -noascend

// Read golden and revised designs
read design -file lec/TOP.vlc -verilog \
 	C:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v \
 	./pci_out_reg.v \
 	./pci_constants.v \
 	./pci_user_constants.v \
 	./pci_rst_int.v \
 	./pci_async_reset_flop.v \
 	./pci_wb_slave.v \
 	./bus_commands.v \
 	./pci_wb_tpram.v \
 	./pci_synchronizer_flop.v \
 	./pci_wbw_fifo_control.v \
 	./pci_wbr_fifo_control.v \
 	./pci_wbw_wbr_fifos.v \
 	./pci_wb_decoder.v \
 	./pci_wb_addr_mux.v \
 	./pci_delayed_sync.v \
 	./pci_delayed_write_reg.v \
 	./pci_master32_sm_if.v \
 	./pci_frame_crit.v \
 	./pci_frame_load_crit.v \
 	./pci_irdy_out_crit.v \
 	./pci_mas_ad_load_crit.v \
 	./pci_mas_ch_state_crit.v \
 	./pci_mas_ad_en_crit.v \
 	./pci_cbe_en_crit.v \
 	./pci_frame_en_crit.v \
 	./pci_master32_sm.v \
 	./pci_wb_slave_unit.v \
 	./pci_wb_master.v \
 	./pci_pci_tpram.v \
 	./pci_pciw_fifo_control.v \
 	./pci_pcir_fifo_control.v \
 	./pci_pciw_pcir_fifos.v \
 	./pci_pci_decoder.v \
 	./pci_target32_interface.v \
 	./pci_target32_clk_en.v \
 	./pci_target32_trdy_crit.v \
 	./pci_target32_stop_crit.v \
 	./pci_target32_devs_crit.v \
 	./pci_target32_sm.v \
 	./pci_target_unit.v \
 	./pci_sync_module.v \
 	./pci_conf_space.v \
 	./pci_io_mux_ad_en_crit.v \
 	./pci_io_mux_ad_load_crit.v \
 	./pci_io_mux.v \
 	./pci_cur_out_reg.v \
 	./pci_par_crit.v \
 	./pci_perr_crit.v \
 	./pci_perr_en_crit.v \
 	./pci_serr_en_crit.v \
 	./pci_serr_crit.v \
 	./pci_parity_check.v \
 	./pci_in_reg.v \
 	./pci_bridge32.v \
 	./WB_Slave.v \
 	./WB_Master.v \
 	./top.v \
	-golden -root TOP
read design -file lec/TOP.vlc -verilog TOP.vm -revised -root TOP

// Generate parsing report
report messages
report black box
report design data
report floating signals

// Read FSM encoding
read fsm encoding lec/c_state_0.vfc
read fsm encoding lec/c_state_1.vfc
read fsm encoding lec/cur_state_2.vfc
read fsm encoding lec/c_state_3.vfc
read fsm encoding lec/c_state_4.vfc
read fsm encoding lec/c_state_5.vfc
read fsm encoding lec/state_6.vfc

// Read setup constraints
read setup file lec/TOP.vsc

// Set mapping options
add renaming rule rulerr "\/Q_r_e_g" "" -revised
add renaming rule rulegh "_Z\[%d\]\[%d\]" "_@1__Z[@2]" -golden
add renaming rule rulegt "_Z\[%d\]$" "[@1]" -type DFF -type DLAT -golden
add renaming rule rulert "_Z\[%d\]$" "[@1]" -type DFF -type DLAT -revised
add renaming rule rulego "_Z$" "" -type DFF -type DLAT -golden
add renaming rule rulero "_Z$" "" -type DFF -type DLAT -revised
set flatten model -seq_constant
// set flatten model -mux_loop_to_dlat
// set flatten model -all_seq_merge
// set flatten model -self_seq_merge
set mapping method -name first

// Run equivalence checker
set sys mode lec -nomap
read map point lec/TOP.vmc
map key point
add compare point -all
compare
usage
// exit -f