timescale.v
来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· Verilog 代码 · 共 19 行
V
19 行
////////////////////////////////////////////////////////////////////////// //////// File name "timescale.v" //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: timescale.v,v $// Revision 1.2 2002/02/01 15:25:13 mihad// Repaired a few bugs, updated specification, added test bench files and design document//// Revision 1.1 2001/10/05 08:11:22 mihad// Updated all files with inclusion of timescale file for simulation purposes.////// timescale directive is included in all core's modules for simulation purposes`timescale 1ns/1ps
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?