top.plg

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· PLG 代码 · 共 18 行

@P:  Worst Slack : 979.673
@P:  TOP|CLK - Estimated Frequency : 49.2 MHz
@P:  TOP|CLK - Requested Frequency : 1.0 MHz
@P:  TOP|CLK - Estimated Period : 20.327
@P:  TOP|CLK - Requested Period : 1000.000
@P:  TOP|CLK - Slack : 979.673
@P:  System - Estimated Frequency : 145.7 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 6.865
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 993.135
@P: TOP Part : xc2s200pq208-6
@P: TOP I/O primitives : 87
@P: TOP I/O Register bits : 0
@P: TOP Register bits (Non I/O) : 1645 (34%)
@P: TOP Block Rams : 6 of 14 (42%)
@P: TOP Total Luts : 1784 (37%)