pci_bridge32.plg

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· PLG 代码 · 共 23 行

@P:  Worst Slack : 977.551
@P:  pci_bridge32|pci_clk_i - Estimated Frequency : 54.8 MHz
@P:  pci_bridge32|pci_clk_i - Requested Frequency : 1.0 MHz
@P:  pci_bridge32|pci_clk_i - Estimated Period : 18.259
@P:  pci_bridge32|pci_clk_i - Requested Period : 1000.000
@P:  pci_bridge32|pci_clk_i - Slack : 981.741
@P:  pci_bridge32|wb_clk_i - Estimated Frequency : 44.5 MHz
@P:  pci_bridge32|wb_clk_i - Requested Frequency : 1.0 MHz
@P:  pci_bridge32|wb_clk_i - Estimated Period : 22.449
@P:  pci_bridge32|wb_clk_i - Requested Period : 1000.000
@P:  pci_bridge32|wb_clk_i - Slack : 977.551
@P:  System - Estimated Frequency : 69.8 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 14.336
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 985.664
@P: pci_bridge32 Part : xc2s200pq208-6
@P: pci_bridge32 I/O primitives : 361
@P: pci_bridge32 I/O Register bits : 0
@P: pci_bridge32 Register bits (Non I/O) : 1520 (32%)
@P: pci_bridge32 Block Rams : 6 of 14 (42%)
@P: pci_bridge32 Total Luts : 1770 (37%)