wb_master.v

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

module WB_Master(
// Clock and reset
    wb_clk_i, wb_rst_i,wb_int_o,

// WISHBONE Master I/F
    wbm_cyc_o ,
    wbm_stb_o ,
    wbm_sel_o ,
    wbm_we_o  ,
    wbm_adr_o ,
    wbm_dat_o ,		
    wbm_cab_o ,
//    wbm_cti_o ,
//    wbm_bte_o ,
    wbm_dat_i ,
    wbm_ack_i ,
    wbm_err_i ,
    wbm_rty_i ,

// User Control From WB_Slave Module, which maybe in another clock zone
	dma_base_addr_i,
	dma_length_i,
	dma_rw_i,
	dma_start_i,
	dma_state_o,

// sram ports
	sram_addr_o,
	sram_data_i,
	sram_data_o,
	sram_oe_o,
	sram_we_o,
	sram_ce_o,
	sram_bhe_o,
	sram_ble_o
);

// Clock and reset
input	    wb_clk_i;	
input	    wb_rst_i;	
output        wb_int_o; 

//  WISHBONE Master I/F
output        wbm_cyc_o,
              wbm_stb_o,
              wbm_we_o;
output [3:0]  wbm_sel_o;
output [31:0] wbm_adr_o;
output [31:0] wbm_dat_o;
output        wbm_cab_o;
//output [2:0]  wbm_cti_o;
//output [1:0]  wbm_bte_o;

input  [31:0] wbm_dat_i;
input         wbm_ack_i, wbm_err_i, wbm_rty_i;

// User Control From WB_Slave Module
input	[31:0]	dma_base_addr_i;
input	[16:0]	dma_length_i; 				//128k Bytes
input			dma_rw_i;					//read to computer = 1, write from computer = 0
input			dma_start_i;
output	[31:0]		dma_state_o;

// sram ports
output	[15:0]	sram_addr_o;
input	[15:0]	sram_data_i;
output	[15:0]	sram_data_o;
output	sram_oe_o;
output	sram_we_o;
output	sram_ce_o;
output	sram_bhe_o;
output	sram_ble_o;

//================ Synchronize the Input =================
reg		[31:0]	dma_base_addr_sync1,dma_base_addr;	//Dwords
reg		[16:0]	dma_length_sync1, dma_length;	  	//sram size is 64k words,32k Dwords
reg				dma_rw_sync1,dma_rw;

always @ (posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		dma_base_addr_sync1 <= 30'h0;	
		dma_base_addr <= 30'h0;

		dma_length_sync1 <= 15'h0;
		dma_length <= 15'h0;

		dma_rw_sync1 <= 1'b0;
		dma_rw <= 1'b0;
	end else begin
		if (!dma_start_i) begin
			dma_base_addr_sync1 <= dma_base_addr_i;	
			dma_base_addr <= dma_base_addr_sync1;

			dma_length_sync1 <= dma_length_i;
			dma_length <= dma_length_sync1;

			dma_rw_sync1 <= dma_rw_i;
			dma_rw <= dma_rw_sync1;
		end
	end
end

//================ WishBone Master Control ==============
parameter STATE_STOP = 2'b00, STATE_WAIT = 2'b01, STATE_DUMPDATA = 2'b10, STATE_FINISH = 2'b11;

reg [1:0] state;
reg [15:0] sram_addr_o;

always @ (posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		state <= STATE_STOP;
	end else begin
		case(state)
			STATE_STOP:
			begin
				if (dma_start_i) begin
					if (dma_rw == 1)	//to computer
						state <= STATE_DUMPDATA;
					else				//from computer
						state <= STATE_WAIT;
				end 
			end
			STATE_WAIT:			
			begin
				if (~dma_start_i) begin
					state <= STATE_STOP;
				end else if (wbm_ack_i) begin
				   	if (sram_addr_o < dma_length[16:1])
						state <= STATE_DUMPDATA;
					else
						state <= STATE_FINISH;
				end
			end
			STATE_DUMPDATA:			
			begin
				if (~dma_start_i) begin
					state <= STATE_STOP;
				end else begin
					state <= STATE_WAIT;
				end
			end
			STATE_FINISH:
			begin
				if (~dma_start_i) state <= STATE_STOP;
			end
		endcase
	end
end

always @ (posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		sram_addr_o <= 16'h0;
	end else begin
		if (state == STATE_STOP) begin
			sram_addr_o <= 16'h0;
		end else if ((state == STATE_WAIT && wbm_ack_i) || state == STATE_DUMPDATA) begin
			sram_addr_o <= sram_addr_o + 1;
		end
	end
end

reg [31:16] reg_wbm_dat_i_h;
always @ (posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		reg_wbm_dat_i_h <= 16'h0;
	end else begin
		if (state == STATE_WAIT && wbm_ack_i && dma_rw == 0)	//from computer
			reg_wbm_dat_i_h <= wbm_dat_i[31:16];
	end
end
assign sram_data_o = (state == STATE_WAIT) ? wbm_dat_i[15:0] : reg_wbm_dat_i_h;
assign sram_ce_o = 1'b0;
assign sram_oe_o = ~dma_rw;
assign sram_we_o = (dma_rw == 0 && ((state == STATE_WAIT && wbm_ack_i == 1) || state == STATE_DUMPDATA)) ? wb_clk_i : 1'b0;
assign sram_bhe_o = 0;
assign sram_ble_o = 0;

reg [15:0] reg_wbm_dat_o_l;
always @ (posedge wb_clk_i or posedge wb_rst_i) begin
	if (wb_rst_i) begin
		reg_wbm_dat_o_l <= 16'h0;
	end else begin
		if (state == STATE_DUMPDATA && wbm_ack_i && dma_rw == 1) //to computer
			reg_wbm_dat_o_l <= sram_data_i;
	end
end
assign wbm_dat_o = {sram_data_i,reg_wbm_dat_o_l};
assign wbm_adr_o = {(dma_base_addr + sram_addr_o[15:1]),2'b0};
assign wbm_cyc_o = (dma_start_i && state != STATE_FINISH);
assign wbm_stb_o = (state == STATE_WAIT);
assign wbm_we_o = dma_rw;
assign wbm_sel_o = 4'b1111;

assign wbm_cab_o = 1'b1;			//PCI Burst Control

//assign wbm_cti_o = 3'b000;		//only used in WISHBONE Rev.B3
//assign wbm_bte_o = 2'b00; 		//only used in WISHBONE Rev.B3

assign wb_int_o = (state == STATE_FINISH);
assign dma_finish_o = wb_int_o;
assign dma_state_o = {10'h0,sram_addr_o,wbm_rty_i,wbm_err_i,state,dma_start_i};
endmodule