wbs_uart.edn

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

(edif wbs_uart
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2004 5 20 16 21 56)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "7.3, Build 170R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell RAM16X1D (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DPO (direction OUTPUT))
           (port SPO (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
           (port A3 (direction INPUT))
           (port D (direction INPUT))
           (port DPRA0 (direction INPUT))
           (port DPRA1 (direction INPUT))
           (port DPRA2 (direction INPUT))
           (port DPRA3 (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MULT_AND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell XORCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port LI (direction INPUT))
           (port CI (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXCY_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell MUXCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXF6 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXF5 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
         )
       )
    )
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDPE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDCE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell raminfr_4_8_16_1 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename bottom "bottom[3:0]") 4) (direction INPUT))
           (port (array (rename rf_data_in "rf_data_in[10:3]") 8) (direction INPUT))
           (port (array (rename top "top[3:0]") 4) (direction INPUT))
           (port (array (rename rf_data_out "rf_data_out[10:3]") 8) (direction OUTPUT))
           (port rf_push_pulse (direction INPUT))
           (port wb_clk_i_c (direction INPUT))
         )
         (contents
          (instance (rename ram_I_8 "ram.I_8") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_7 "ram.I_7") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_6 "ram.I_6") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_5 "ram.I_5") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_4 "ram.I_4") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_3 "ram.I_3") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_2 "ram.I_2") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (instance (rename ram_I_1 "ram.I_1") (viewRef PRIM (cellRef RAM16X1D (libraryRef VIRTEX)))
          )
          (net (rename bottom_0 "bottom[0]") (joined
           (portRef (member bottom 3))
           (portRef DPRA0 (instanceRef ram_I_1))
           (portRef DPRA0 (instanceRef ram_I_2))
           (portRef DPRA0 (instanceRef ram_I_3))
           (portRef DPRA0 (instanceRef ram_I_4))
           (portRef DPRA0 (instanceRef ram_I_5))
           (portRef DPRA0 (instanceRef ram_I_6))
           (portRef DPRA0 (instanceRef ram_I_7))
           (portRef DPRA0 (instanceRef ram_I_8))
          ))
          (net (rename bottom_1 "bottom[1]") (joined
           (portRef (member bottom 2))
           (portRef DPRA1 (instanceRef ram_I_1))
           (portRef DPRA1 (instanceRef ram_I_2))
           (portRef DPRA1 (instanceRef ram_I_3))
           (portRef DPRA1 (instanceRef ram_I_4))
           (portRef DPRA1 (instanceRef ram_I_5))
           (portRef DPRA1 (instanceRef ram_I_6))
           (portRef DPRA1 (instanceRef ram_I_7))
           (portRef DPRA1 (instanceRef ram_I_8))
          ))
          (net (rename bottom_2 "bottom[2]") (joined
           (portRef (member bottom 1))
           (portRef DPRA2 (instanceRef ram_I_1))
           (portRef DPRA2 (instanceRef ram_I_2))
           (portRef DPRA2 (instanceRef ram_I_3))
           (portRef DPRA2 (instanceRef ram_I_4))
           (portRef DPRA2 (instanceRef ram_I_5))
           (portRef DPRA2 (instanceRef ram_I_6))
           (portRef DPRA2 (instanceRef ram_I_7))
           (portRef DPRA2 (instanceRef ram_I_8))
          ))
          (net (rename bottom_3 "bottom[3]") (joined
           (portRef (member bottom 0))
           (portRef DPRA3 (instanceRef ram_I_1))
           (portRef DPRA3 (instanceRef ram_I_2))
           (portRef DPRA3 (instanceRef ram_I_3))
           (portRef DPRA3 (instanceRef ram_I_4))
           (portRef DPRA3 (instanceRef ram_I_5))
           (portRef DPRA3 (instanceRef ram_I_6))