wbs_uart.tlg

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

Selecting top level module wbs_uart
Synthesizing module uart_wb
@N:"E:\ISEprog\pcibridgeguest_uart\uart_wb.v":195:0:195:5|Trying to extract state machine for register wbstate
Extracted state machine for register wbstate
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Synthesizing module raminfr
	addr_width=32'b00000000000000000000000000000100
	data_width=32'b00000000000000000000000000001000
	depth=32'b00000000000000000000000000010000
   Generated name = raminfr_4_8_16
@N:"E:\ISEprog\pcibridgeguest_uart\raminfr.v":112:15:112:23|Found RAM ram, depth=16, width=8
Synthesizing module uart_tfifo
Synthesizing module uart_transmitter
@N:"E:\ISEprog\pcibridgeguest_uart\uart_transmitter.v":213:0:213:5|Trying to extract state machine for register tstate
Extracted state machine for register tstate
State machine has 6 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
Synthesizing module uart_rfifo
	fifo_width=32'b00000000000000000000000000001011
	fifo_depth=32'b00000000000000000000000000010000
	fifo_pointer_w=32'b00000000000000000000000000000100
	fifo_counter_w=32'b00000000000000000000000000000101
   Generated name = uart_rfifo_11_16_4_5
Synthesizing module uart_receiver
@N:"E:\ISEprog\pcibridgeguest_uart\uart_receiver.v":275:0:275:5|Trying to extract state machine for register rstate
Extracted state machine for register rstate
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
Synthesizing module uart_regs
Synthesizing module uart_debug_if
Synthesizing module uart_top
@W:"E:\ISEprog\pcibridgeguest_uart\uart_top.v":327:0:327:6|Ignoring initial statement
Synthesizing module wbs_uart
@W:"E:\ISEprog\pcibridgeguest_uart\wbs_uart.v":75:10:75:21|*Input cts_pad_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:"E:\ISEprog\pcibridgeguest_uart\wbs_uart.v":75:10:75:21|*Input dsr_pad_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:"E:\ISEprog\pcibridgeguest_uart\wbs_uart.v":75:10:75:21|*Input ri_pad_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:"E:\ISEprog\pcibridgeguest_uart\wbs_uart.v":75:10:75:21|*Input dcd_pad_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:"E:\ISEprog\pcibridgeguest_uart\wbs_uart.v":30:8:30:16|Input wbs_cti_i is unused
@W:"E:\ISEprog\pcibridgeguest_uart\wbs_uart.v":30:18:30:26|Input wbs_bte_i is unused