dpramb.edn

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 2 20 14 16 51)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 5.2i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2002 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_reg_inputsb = 0 ")
       (comment "c_reg_inputsa = 0 ")
       (comment "c_has_ndb = 0 ")
       (comment "c_has_nda = 0 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_has_rfdb = 0 ")
       (comment "c_has_rfda = 0 ")
       (comment "c_ywea_is_high = 1 ")
       (comment "c_yena_is_high = 1 ")
       (comment "InstanceName = dpramb ")
       (comment "c_yclka_is_rising = 1 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_family = virtex ")
       (comment "c_ysinita_is_high = 1 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_width_b = 8 ")
       (comment "c_width_a = 8 ")
       (comment "c_sinita_value = 0 ")
       (comment "c_sinitb_value = 0 ")
       (comment "c_limit_data_pitch = 18 ")
       (comment "c_write_modeb = 0 ")
       (comment "c_write_modea = 0 ")
       (comment "c_has_rdyb = 0 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_rdya = 0 ")
       (comment "c_addra_width = 7 ")
       (comment "c_addrb_width = 7 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_default_data = 0 ")
       (comment "c_pipe_stages_b = 0 ")
       (comment "c_yweb_is_high = 1 ")
       (comment "c_yenb_is_high = 1 ")
       (comment "c_pipe_stages_a = 0 ")
       (comment "c_yclkb_is_rising = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_ysinitb_is_high = 1 ")
       (comment "c_has_web = 1 ")
       (comment "c_has_default_data = 1 ")
       (comment "c_has_sinitb = 0 ")
       (comment "c_has_wea = 1 ")
       (comment "c_has_sinita = 0 ")
       (comment "c_has_dinb = 1 ")
       (comment "c_has_dina = 1 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_has_enb = 1 ")
       (comment "c_has_ena = 1 ")
       (comment "c_depth_b = 128 ")
       (comment "c_mem_init_file = mif_file_16_1 ")
       (comment "c_depth_a = 128 ")
       (comment "c_has_doutb = 1 ")
       (comment "c_has_douta = 1 ")
       (comment "c_yprimitive_type = 4kx1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell RAMB4_S8_S8 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WEA (direction INPUT))
                   (port ENA (direction INPUT))
                   (port RSTA (direction INPUT))
                   (port CLKA (direction INPUT))
                   (port (rename DIA_0_ "DIA<0>") (direction INPUT))
                   (port (rename DIA_1_ "DIA<1>") (direction INPUT))
                   (port (rename DIA_2_ "DIA<2>") (direction INPUT))
                   (port (rename DIA_3_ "DIA<3>") (direction INPUT))
                   (port (rename DIA_4_ "DIA<4>") (direction INPUT))
                   (port (rename DIA_5_ "DIA<5>") (direction INPUT))
                   (port (rename DIA_6_ "DIA<6>") (direction INPUT))
                   (port (rename DIA_7_ "DIA<7>") (direction INPUT))
                   (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
                   (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
                   (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
                   (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
                   (port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
                   (port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
                   (port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
                   (port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
                   (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
                   (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
                   (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
                   (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
                   (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
                   (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
                   (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
                   (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
                   (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
                   (port WEB (direction INPUT))
                   (port ENB (direction INPUT))
                   (port RSTB (direction INPUT))
                   (port CLKB (direction INPUT))
                   (port (rename DIB_0_ "DIB<0>") (direction INPUT))
                   (port (rename DIB_1_ "DIB<1>") (direction INPUT))
                   (port (rename DIB_2_ "DIB<2>") (direction INPUT))
                   (port (rename DIB_3_ "DIB<3>") (direction INPUT))
                   (port (rename DIB_4_ "DIB<4>") (direction INPUT))
                   (port (rename DIB_5_ "DIB<5>") (direction INPUT))
                   (port (rename DIB_6_ "DIB<6>") (direction INPUT))
                   (port (rename DIB_7_ "DIB<7>") (direction INPUT))
                   (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
                   (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
                   (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
                   (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
                   (port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
                   (port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
                   (port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
                   (port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
                   (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
                   (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
                   (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
                   (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
                   (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
                   (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
                   (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
                   (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
                   (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell dpramb
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename addra_6_ "addra<6>") (direction INPUT))
   (port ( rename addra_5_ "addra<5>") (direction INPUT))
   (port ( rename addra_4_ "addra<4>") (direction INPUT))
   (port ( rename addra_3_ "addra<3>") (direction INPUT))
   (port ( rename addra_2_ "addra<2>") (direction INPUT))
   (port ( rename addra_1_ "addra<1>") (direction INPUT))
   (port ( rename addra_0_ "addra<0>") (direction INPUT))
   (port ( rename addrb_6_ "addrb<6>") (direction INPUT))
   (port ( rename addrb_5_ "addrb<5>") (direction INPUT))
   (port ( rename addrb_4_ "addrb<4>") (direction INPUT))
   (port ( rename addrb_3_ "addrb<3>") (direction INPUT))
   (port ( rename addrb_2_ "addrb<2>") (direction INPUT))
   (port ( rename addrb_1_ "addrb<1>") (direction INPUT))
   (port ( rename addrb_0_ "addrb<0>") (direction INPUT))
   (port ( rename clka "clka") (direction INPUT))
   (port ( rename clkb "clkb") (direction INPUT))
   (port ( rename dina_7_ "dina<7>") (direction INPUT))
   (port ( rename dina_6_ "dina<6>") (direction INPUT))
   (port ( rename dina_5_ "dina<5>") (direction INPUT))
   (port ( rename dina_4_ "dina<4>") (direction INPUT))
   (port ( rename dina_3_ "dina<3>") (direction INPUT))
   (port ( rename dina_2_ "dina<2>") (direction INPUT))
   (port ( rename dina_1_ "dina<1>") (direction INPUT))
   (port ( rename dina_0_ "dina<0>") (direction INPUT))
   (port ( rename dinb_7_ "dinb<7>") (direction INPUT))
   (port ( rename dinb_6_ "dinb<6>") (direction INPUT))
   (port ( rename dinb_5_ "dinb<5>") (direction INPUT))
   (port ( rename dinb_4_ "dinb<4>") (direction INPUT))
   (port ( rename dinb_3_ "dinb<3>") (direction INPUT))
   (port ( rename dinb_2_ "dinb<2>") (direction INPUT))
   (port ( rename dinb_1_ "dinb<1>") (direction INPUT))
   (port ( rename dinb_0_ "dinb<0>") (direction INPUT))
   (port ( rename ena "ena") (direction INPUT))
   (port ( rename enb "enb") (direction INPUT))
   (port ( rename wea "wea") (direction INPUT))
   (port ( rename web "web") (direction INPUT))
   (port ( rename douta_7_ "douta<7>") (direction OUTPUT))
   (port ( rename douta_6_ "douta<6>") (direction OUTPUT))
   (port ( rename douta_5_ "douta<5>") (direction OUTPUT))
   (port ( rename douta_4_ "douta<4>") (direction OUTPUT))
   (port ( rename douta_3_ "douta<3>") (direction OUTPUT))
   (port ( rename douta_2_ "douta<2>") (direction OUTPUT))
   (port ( rename douta_1_ "douta<1>") (direction OUTPUT))
   (port ( rename douta_0_ "douta<0>") (direction OUTPUT))
   (port ( rename doutb_7_ "doutb<7>") (direction OUTPUT))
   (port ( rename doutb_6_ "doutb<6>") (direction OUTPUT))
   (port ( rename doutb_5_ "doutb<5>") (direction OUTPUT))
   (port ( rename doutb_4_ "doutb<4>") (direction OUTPUT))
   (port ( rename doutb_3_ "doutb<3>") (direction OUTPUT))
   (port ( rename doutb_2_ "doutb<2>") (direction OUTPUT))
   (port ( rename doutb_1_ "doutb<1>") (direction OUTPUT))
   (port ( rename doutb_0_ "doutb<0>") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance B5
      (viewRef view_1 (cellRef RAMB4_S8_S8 (libraryRef xilinxun)))
      (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef RSTA (instanceRef B5))
      (portRef RSTB (instanceRef B5))
      (portRef ADDRA_7_ (instanceRef B5))
      (portRef ADDRA_8_ (instanceRef B5))
      (portRef ADDRB_7_ (instanceRef B5))
      (portRef ADDRB_8_ (instanceRef B5))
    )
   )
   (net (rename N18 "douta<7>")
    (joined
      (portRef douta_7_)
      (portRef DOA_7_ (instanceRef B5))
    )
   )
   (net (rename N19 "douta<6>")
    (joined
      (portRef douta_6_)
      (portRef DOA_6_ (instanceRef B5))
    )
   )
   (net (rename N20 "douta<5>")
    (joined
      (portRef douta_5_)
      (portRef DOA_5_ (instanceRef B5))
    )
   )
   (net (rename N21 "douta<4>")
    (joined
      (portRef douta_4_)
      (portRef DOA_4_ (instanceRef B5))
    )
   )
   (net (rename N22 "douta<3>")
    (joined
      (portRef douta_3_)
      (portRef DOA_3_ (instanceRef B5))
    )
   )