mvbif.twr

MVBC VHDL代码．．实现多功能车辆总线的通信

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml mvbif mvbif.ncd -o
mvbif.twr mvbif.pcf


Design file:              mvbif.ncd
Physical constraint file: mvbif.pcf
Device,speed:             xc2s300e,-6 (PRODUCTION 1.17 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
addr_cpu<0> |    2.447(R)|   -1.889(R)|clk_BUFGP         |   0.000|
addr_cpu<10>|    1.200(R)|   -0.048(R)|clk_BUFGP         |   0.000|
addr_cpu<11>|    1.185(R)|   -0.033(R)|clk_BUFGP         |   0.000|
addr_cpu<12>|    0.508(R)|    0.050(R)|clk_BUFGP         |   0.000|
addr_cpu<13>|    1.752(R)|   -1.194(R)|clk_BUFGP         |   0.000|
addr_cpu<14>|    2.450(R)|   -1.892(R)|clk_BUFGP         |   0.000|
addr_cpu<15>|    2.982(R)|   -2.424(R)|clk_BUFGP         |   0.000|
addr_cpu<16>|    2.675(R)|   -2.117(R)|clk_BUFGP         |   0.000|
addr_cpu<17>|    1.628(R)|   -1.070(R)|clk_BUFGP         |   0.000|
addr_cpu<18>|    1.385(R)|   -0.827(R)|clk_BUFGP         |   0.000|
addr_cpu<19>|    0.907(R)|   -0.349(R)|clk_BUFGP         |   0.000|
addr_cpu<1> |    3.234(R)|   -2.676(R)|clk_BUFGP         |   0.000|
addr_cpu<20>|    3.326(R)|   -2.768(R)|clk_BUFGP         |   0.000|
addr_cpu<21>|    2.738(R)|   -2.180(R)|clk_BUFGP         |   0.000|
addr_cpu<22>|    2.836(R)|   -2.278(R)|clk_BUFGP         |   0.000|
addr_cpu<23>|    2.462(R)|   -1.904(R)|clk_BUFGP         |   0.000|
addr_cpu<2> |    2.871(R)|   -2.313(R)|clk_BUFGP         |   0.000|
addr_cpu<3> |    2.216(R)|   -1.658(R)|clk_BUFGP         |   0.000|
addr_cpu<4> |    2.721(R)|   -2.163(R)|clk_BUFGP         |   0.000|
addr_cpu<5> |    3.183(R)|   -2.625(R)|clk_BUFGP         |   0.000|
addr_cpu<6> |    2.634(R)|   -2.076(R)|clk_BUFGP         |   0.000|
addr_cpu<7> |    1.438(R)|   -0.880(R)|clk_BUFGP         |   0.000|
addr_cpu<8> |    0.551(R)|    0.007(R)|clk_BUFGP         |   0.000|
addr_cpu<9> |    1.256(R)|   -0.104(R)|clk_BUFGP         |   0.000|
cs_cpu_n    |    2.788(R)|   -0.073(R)|clk_BUFGP         |   0.000|
oe_cpu_n    |    1.241(R)|   -0.089(R)|clk_BUFGP         |   0.000|
wr_cpu_n    |    1.200(R)|   -0.048(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
-------------+------------+------------------+--------+
             | clk (edge) |                  |  Clock |
Destination  | to PAD     |Internal Clock(s) |  Phase |
-------------+------------+------------------+--------+
addr_mvbc<0> |    6.556(R)|clk_BUFGP         |   0.000|
addr_mvbc<10>|    9.043(R)|clk_BUFGP         |   0.000|
addr_mvbc<11>|    9.793(R)|clk_BUFGP         |   0.000|
addr_mvbc<12>|    6.500(R)|clk_BUFGP         |   0.000|
addr_mvbc<13>|    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<14>|    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<15>|    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<16>|    6.556(R)|clk_BUFGP         |   0.000|
addr_mvbc<17>|    6.500(R)|clk_BUFGP         |   0.000|
addr_mvbc<18>|    6.500(R)|clk_BUFGP         |   0.000|
addr_mvbc<19>|    6.556(R)|clk_BUFGP         |   0.000|
addr_mvbc<1> |    6.485(R)|clk_BUFGP         |   0.000|
addr_mvbc<20>|    6.485(R)|clk_BUFGP         |   0.000|
addr_mvbc<21>|    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<22>|    6.556(R)|clk_BUFGP         |   0.000|
addr_mvbc<23>|    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<2> |    6.500(R)|clk_BUFGP         |   0.000|
addr_mvbc<3> |    6.500(R)|clk_BUFGP         |   0.000|
addr_mvbc<4> |    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<5> |    6.541(R)|clk_BUFGP         |   0.000|
addr_mvbc<6> |    6.556(R)|clk_BUFGP         |   0.000|
addr_mvbc<7> |    6.500(R)|clk_BUFGP         |   0.000|
addr_mvbc<8> |    6.485(R)|clk_BUFGP         |   0.000|
addr_mvbc<9> |    9.269(R)|clk_BUFGP         |   0.000|
cs_mvbc_n    |    8.530(R)|clk_BUFGP         |   0.000|
rd_mvbc_n    |    9.223(R)|clk_BUFGP         |   0.000|
rdy2cpu_n    |    6.541(R)|clk_BUFGP         |   0.000|
wr_mvbc_n    |    9.946(R)|clk_BUFGP         |   0.000|
-------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    3.480|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
CS<0>          |SPARE0         |   13.190|
CS<1>          |SPARE0         |   13.193|
CS<2>          |SPARE0         |   13.956|
CS<3>          |SPARE0         |   13.813|
CS<4>          |SPARE0         |    9.466|
CS<5>          |SPARE0         |    9.438|
CS<6>          |SPARE0         |   10.060|
cs_cpu_n       |SPARE0         |    9.913|
int_mvbc0_n    |int_cpu0_n     |    5.847|
int_mvbc1_n    |int_cpu1_n     |    6.276|
rst            |rst_mvbc       |    6.010|
---------------+---------------+---------+

Analysis completed Wed Jan 10 15:30:39 2007
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Peak Memory Usage: 54 MB