mvbiffff.v

来自「MVBC VHDL代码．．实现多功能车辆总线的通信」· Verilog 代码 · 共 144 行

module mvbif(	clk, rst, cs_cpu_n, int_mvbc0_n, int_mvbc1_n,wr_cpu_n, 
            	oe_cpu_n, addr_cpu, rdy2mvbc_n,CS,
               addr_mvbc,  rdy2cpu_n, rst_mvbc, wr_mvbc_n, 
               rd_mvbc_n, cs_mvbc_n,  int_cpu0_n, int_cpu1_n,
			JTEG_EN,SPARE0);
    input clk;
    input rst;
    input cs_cpu_n;
    input int_mvbc0_n;
    input int_mvbc1_n;
    input wr_cpu_n;
    input oe_cpu_n;
    input [23:0] addr_cpu;
    input rdy2mvbc_n;

	input  [6:0]CS;
	output JTEG_EN;
	output SPARE0;

    output rdy2cpu_n;
    output rst_mvbc;
    output wr_mvbc_n;
    output rd_mvbc_n;
    output cs_mvbc_n;
    output int_cpu0_n;
    output int_cpu1_n;
    output [23:0] addr_mvbc;

    reg rdy2cpu_n;
    //reg rst_mvbc;
    reg wr_mvbc_n;
    reg rd_mvbc_n;
    reg cs_mvbc_n;
    //reg int_cpu0_n;
    //reg int_cpu1_n;
    reg [23:0] addr_mvbc;

	 reg [2:0] counter;
	 reg  Delay;
    reg overflow;
	 ////////////////////////////
  

	assign SPARE0=CS[0]&CS[1]&CS[2]&CS[3]&CS[4]&CS[5]&CS[6]&cs_cpu_n;
	assign JTEG_EN=0;
	assign int_cpu0_n = int_mvbc0_n;
     assign int_cpu1_n = int_mvbc1_n;

/*
     assign wr_mvbc_n = wr_cpu_n;
     assign rd_mvbc_n = oe_cpu_n ;
     assign cs_mvbc_n = cs_cpu_n;
	assign addr_mvbc = addr_cpu; 
*/
	assign rst_mvbc  = rst;

/*
	always@(cs_cpu_n)
	begin
		if(!cs_cpu_n) 
			rdy2cpu_n=rdy2mvbc_n;
		else
			rdy2cpu_n=1;
	end
*/	

	always@(posedge clk )
	begin
		//rst_mvbc <= rst;
		wr_mvbc_n <= wr_cpu_n;
		rd_mvbc_n <= oe_cpu_n ;
		cs_mvbc_n <= cs_cpu_n;
		//int_cpu0_n <= int_mvbc0_n;
		//int_cpu1_n <= int_mvbc1_n;
		addr_mvbc <= addr_cpu; 
	end
	 
///////////////////////////////////////////////////////////////////////////////////////////////////	
/*	always@(posedge clk )
	begin
	if(!cs_cpu_n)
		begin
		if(!rst )
			rdy2cpu_n<=0;
		else
	 		begin
			if( rdy2mvbc_n | Delay)
			rdy2cpu_n<=1;
			else
			rdy2cpu_n<=0;
			end
		end
	else
		rdy2cpu_n<=1;
	end


	always@(posedge clk )
	 if( !rst | overflow )
	  Delay<=0;
	 else
	  if( rdy2mvbc_n )
	  	Delay<=1;
 	 */
////////////////////////////////////////////////////////////////////////////////////////////////
   always@(posedge clk )
	   begin
	 if(Delay & !cs_cpu_n  )
	    begin
	  counter<=counter+1;
	  overflow=counter[2];
	     end
    else
	    begin
	  counter<=0;
	  overflow=counter[2];
	    end
		 end

   
	
	always @ (posedge clk )
	     
	    if( !cs_cpu_n) 
		      Delay=1;
         else
           Delay=0;

		 
    always @( posedge clk)

	     begin

		  if ( !overflow | cs_cpu_n)
		        
				 rdy2cpu_n=1;
				 else
					rdy2cpu_n=0;

			 end

endmodule