📄 mvbc3.gfl

📁 MVBC VHDL代码．．实现多功能车辆总线的通信
💻 GFL
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# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\2006\fpga_design\mvbc3\mvbc3/_ngo
mvbif.ngd
mvbif_ngdbuild.nav
mvbif.bld
.untf
mvbif.cmd_log
# Implementation : Map
mvbif_map.ncd
mvbif.ngm
mvbif.pcf
mvbif.nc1
mvbif.mrp
mvbif_map.mrp
mvbif.mdf
__projnav/map.log
mvbif.cmd_log
MAP_NO_GUIDE_FILE_CPF "mvbif"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mvbif.twr
mvbif.twx
mvbif.tsi
mvbif.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
mvbif.ncd
mvbif.par
mvbif.pad
mvbif_pad.txt
mvbif_pad.csv
mvbif.pad_txt
mvbif.dly
reportgen.log
mvbif.xpi
mvbif.grf
mvbif.itr
mvbif_last_par.ncd
__projnav/par.log
mvbif.placed_ncd_tracker
mvbif.routed_ncd_tracker
mvbif.cmd_log
PAR_NO_GUIDE_FILE_CPF "mvbif"
# ProjNav -> New Source -> TBW
d:\2006\fpga_design\mvbc3\mvbc3\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# Bencher Waveform : PDCL (jhdparse)
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\2006\fpga_design\mvbc3\mvbc3/_ngo
mvbif.ngd
mvbif_ngdbuild.nav
mvbif.bld
.untf
mvbif.cmd_log
# Implementation : Map
mvbif_map.ncd
mvbif.ngm
mvbif.pcf
mvbif.nc1
mvbif.mrp
mvbif_map.mrp
mvbif.mdf
__projnav/map.log
mvbif.cmd_log
MAP_NO_GUIDE_FILE_CPF "mvbif"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mvbif.twr
mvbif.twx
mvbif.tsi
mvbif.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
mvbif.ncd
mvbif.par
mvbif.pad
mvbif_pad.txt
mvbif_pad.csv
mvbif.pad_txt
mvbif.dly
reportgen.log
mvbif.xpi
mvbif.grf
mvbif.itr
mvbif_last_par.ncd
__projnav/par.log
mvbif.placed_ncd_tracker
mvbif.routed_ncd_tracker
mvbif.cmd_log
PAR_NO_GUIDE_FILE_CPF "mvbif"
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\2006\fpga_design\mvbc3\mvbc3/_ngo
mvbif.ngd
mvbif_ngdbuild.nav
mvbif.bld
.untf
mvbif.cmd_log
# Implementation : Map
mvbif_map.ncd
mvbif.ngm
mvbif.pcf
mvbif.nc1
mvbif.mrp
mvbif_map.mrp
mvbif.mdf
__projnav/map.log
mvbif.cmd_log
MAP_NO_GUIDE_FILE_CPF "mvbif"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mvbif.twr
mvbif.twx
mvbif.tsi
mvbif.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
mvbif.ncd
mvbif.par
mvbif.pad
mvbif_pad.txt
mvbif_pad.csv
mvbif.pad_txt
mvbif.dly
reportgen.log
mvbif.xpi
mvbif.grf
mvbif.itr
mvbif_last_par.ncd
__projnav/par.log
mvbif.placed_ncd_tracker
mvbif.routed_ncd_tracker
mvbif.cmd_log
PAR_NO_GUIDE_FILE_CPF "mvbif"
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\2006\fpga_design\mvbc3\mvbc3/_ngo
mvbif.ngd
mvbif_ngdbuild.nav
mvbif.bld
.untf
mvbif.cmd_log
# Implementation : Map
mvbif_map.ncd
mvbif.ngm
mvbif.pcf
mvbif.nc1
mvbif.mrp
mvbif_map.mrp
mvbif.mdf
__projnav/map.log
mvbif.cmd_log
MAP_NO_GUIDE_FILE_CPF "mvbif"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
mvbif.twr
mvbif.twx
mvbif.tsi
mvbif.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
mvbif.ncd
mvbif.par
mvbif.pad
mvbif_pad.txt
mvbif_pad.csv
mvbif.pad_txt
mvbif.dly
reportgen.log
mvbif.xpi
mvbif.grf
mvbif.itr
mvbif_last_par.ncd
__projnav/par.log
mvbif.placed_ncd_tracker
mvbif.routed_ncd_tracker
mvbif.cmd_log
PAR_NO_GUIDE_FILE_CPF "mvbif"
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
mvbif.lso
# xst flow : RunXST
mvbif.syr
mvbif.prj
mvbif.sprj
mvbif.ana
mvbif.stx
mvbif.cmd_log
mvbif.ngc
mvbif.ngr
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# ModelSim : Simulate Behavioral Verilog Model
mvbc3tbw.fdo
# ModelSim : Simulate Behavioral Verilog Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
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