start_xscale.s

一个基于XSCALE的自启动bootloader,包含源代码和下载工具

#include "start_xscale.h"
.text
.extern _ld_text_start
.extern _ld_text_and_data_size

.globl _start
_start:
        b       reset
reset:
	/*Mask All interrupt*/ 
        ldr     r12, =INTERRUPT_CONTROL_BASE
        ldr     r0, =0x00000000
        str     r0, [r12, #ICMR]
        str     r0, [r12, #ICLR]
	/*Initialize GPIO*/
        bl      gpio_init
	/* Initialize SDRAM*/
        bl      init_sdram
	/* Copy Bootloader from Flash to SDRAM*/
	bl	copy_to_ram
	/* Loading kernel image*/
        ldr	r4, =KERNEL_SRAM_BASE
        ldr	r5, =KERNEL_DRAM_BASE
        ldr	r6, =KERNEL_MAX_SIZE
        add	r6, r6, r4
repeat:
        ldmia   r4!, {r0-r3, r7-r10}
        stmia   r5!, {r0-r3, r7-r10}
        cmp             r4, r6
        blt             repeat
	ldr	sp, =_ld_stack_address
	/* Jump to c_main*/
	ldr	r0, =c_main
	mov	pc, r0
die:
	b	die
/*/////////////////////////////////////////////////////////////////////////////
///////////		Initialize GPIO				///////
/////////////////////////////////////////////////////////////////////////////*/
gpio_init:
	ldr     r12, =GPIO_BASE

    ldr     r0, =GAFR0L_VALUE
    str     r0, [r12, #GAFR0_L]
    ldr     r0, =GAFR0U_VALUE
    str     r0, [r12, #GAFR0_U]

    ldr     r0, =GAFR1L_VALUE
    str     r0, [r12, #GAFR1_L]
    ldr     r0, =GAFR1U_VALUE
    str     r0, [r12, #GAFR1_U]

    ldr     r0, =GAFR2L_VALUE
    str     r0, [r12, #GAFR2_L]
    ldr     r0, =GAFR2U_VALUE
    str     r0, [r12, #GAFR2_U]

    ldr     r0, =GPSR0_VALUE
    str     r0, [r12, #GPSR0]
    ldr     r0, =GPSR1_VALUE
    str     r0, [r12, #GPSR1]
    ldr     r0, =GPSR2_VALUE
    str     r0, [r12, #GPSR2]

    ldr     r0, =GPCR0_VALUE
    str     r0, [r12, #GPCR0]
    ldr     r0, =GPCR1_VALUE
    str     r0, [r12, #GPCR1]
    ldr     r0, =GPCR2_VALUE
    str     r0, [r12, #GPCR2]

    ldr     r0, =GPDR0_VALUE
    str     r0, [r12, #GPDR0]
    ldr     r0, =GPDR1_VALUE
    str     r0, [r12, #GPDR1]
    ldr     r0, =GPDR2_VALUE
    str     r0, [r12, #GPDR2]

   /*Save the GPIO config*/
	ldr     r1, =PSSR
	ldr	r2,=0x00000030
	/*ldr     r2, =(PSSR_RDH|PSSR_PH)*/
	str     r2, [r1]
    mov     pc, lr
/*/////////////////////////////////////////////////////////////////////////////
///////////	 	Initialize SDRAM			///////////////
/////////////////////////////////////////////////////////////////////////////*/
init_sdram:
		mov		r10, lr
        ldr     r12, =CLOCK_MANAGER_BASE
/*Set the clock of the memory to 99.53MHz*/
        ldr     r0, =CKEN_VALUE
        str     r0, [r12, #CKEN]
        ldr     r0, =OSCC_VALUE
        str     r0, [r12, #OSCC]
/*Enter frequency change*/
        ldr     r0, =CCCR_VALUE
        str     r0, [r12, #CCCR]
        mov     r1, #3
        mcr     p14, 0, r1, c6, c0, 0
/*Clear the OSCR to restart counting from 0*/
		ldr	r1, =OSCR
		ldr	r0, =0
		str	r0, [r1]
/*delay 200us*/
        ldr     r0, =0x300
wait_for_clock:
        ldr	r2, [r1]
        cmp     r0, r2
        bne     wait_for_clock
	/*Start memory initialize*/
        ldr     r12, =MEM_CTL_BASE
	/*Set the cs[0:5]*/
        ldr     r0, =MSC0_VALUE
        str     r0, [r12, #MSC0]
        ldr     r0, [r12, #MSC0] 	/* reads it back to make sure it works...*/
        ldr     r0, =MSC1_VALUE
        str     r0, [r12, #MSC1]
        ldr     r0, [r12, #MSC1]
        ldr     r0, =MSC2_VALUE
        str     r0, [r12, #MSC2]
        ldr     r0, [r12, #MSC2]

        ldr     r0, =MECR_VALUE
        str     r0, [r12, #MECR]

        ldr     r0, =MCMEM0_VALUE
        str     r0, [r12, #MCMEM0]
        ldr     r0, =MCMEM1_VALUE
        str     r0, [r12, #MCMEM1]

        ldr     r0, =MCATT0_VALUE
        str     r0, [r12, #MCATT0]
        ldr     r0, =MCATT1_VALUE
        str     r0, [r12, #MCATT1]

        ldr     r0, =MCIO0_VALUE
        str     r0, [r12, #MCIO0]
        ldr     r0, =MCIO1_VALUE
        str     r0, [r12, #MCIO1]
     /*Reset the DRI to 0x018*/
        ldr     r0, =MDREFR_VALUE
        ldr     r3, [r12, #MDREFR]
        ldr    r1, =0xFFF
        and    r0, r0, r1
	    bic    r3, r3, r1
		bic	   r3, r3, #0x03800000
        orr     r3, r3, r0
        str     r3, [r12, #MDREFR]  /*Write it back*/
	/*Set the SDCLK*/
        ldr     	r0, =MDREFR_VALUE
		ldr r1, =0xF6000
	/* Mask of SDCLK's settings minus EXPIN*/
		and		r0, r0, r1
        bic  	r3, r3, r1
		orr		r3, r3, r0
        str     	r3, [r12, #MDREFR]
		ldr		r3, [r12, #MDREFR]
	/*close the self-refresh*/
        bic     r3, r3, #0x00400000
        str     r3, [r12, #MDREFR]
	/* Enable the Various SDCLK's and let it run.
	/ Also, enable the free-running clocks .*/
		ldr	r0, =MDREFR_VALUE
		ldr	r1, =0x03809000
		and	r0, r0, r1
		orr	r3, r3, r0
        str     r3, [r12, #MDREFR]
        nop
        nop
    /*Start SDRAM initialize*/
        ldr     r0, =MDCNFG_VALUE
    /*disable all sdram banks*/
        bic     r0, r0, #0x00000003
        bic     r0, r0, #0x00030000
    /*program banks 0/1 for 32 bit bus width*/
        bic     r0, r0, #0x00000004
	    str     r0, [r12, #MDCNFG]
    /*restart counting*/
        ldr     	r0, =OSCR
		mov		r1, #0
		str		r1, [r0]
    /*pause for approx 200 usecs*/
        ldr     r4, =0x300
sdram_dly:
        ldr     r1, [r0]
        cmp     r4, r1
        bgt     sdram_dly
    /*/Enable the data cache and set the data to little endian*/
        mov     r0, #0x78
        mcr     p15, 0, r0, c1, c0, 0
    /*Access memory that has not been enabled for CBR refresh cycles (8)*/
		ldr	r0, =SDRAM_BASE
        str     r0, [r0]
        str     r0, [r0]
        str     r0, [r0]
        str     r0, [r0]
        str     r0, [r0]
        str     r0, [r0]
        str     r0, [r0]
        str     r0, [r0]
        
/*enable bank 0*/
        ldr     r0, [r12, #MDCNFG]
        orr     r0, r0, #0x00000001
        str     r0, [r12, #MDCNFG]
    /*write MDMRS again*/
        ldr     r0, =MDMRS_VALUE
        str     r0, [r12, #MDMRS]
    /*close the auto-power-down*/
        ldr     r0, [r12, #MDREFR]
		ldr	r11, =0xFFEFFFFF
		and	r0, r0, r11
        str     r0, [r12, #MDREFR]
        mov     pc, r10
/*////////////////////////////////////////////////////////////////////////////////////////////
///////////	 Copy Bootloader from Flash to SDRAM	///////////////
////////////////////////////////////////////////////////////////////////////////////////////*/
copy_to_ram:
	mov	r8, lr
	ldr	r0, =0
	ldr	r1, =_ld_text_start
	ldr	r2, =_ld_text_and_data_size
copy_loop:
	ldr	r3, [r0]
	str	r3, [r1]
	add	r0, r0, #4
	add	r1, r1, #4
	subs	r2, r2, #4
	bne	copy_loop
	mov	pc, r8
/*start_xscale end*/