sy3w.vwf

来自「是一个用 maxplus2做的vhdl 很平常的课程小设计」· VWF 代码 · 共 154 行

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 1000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 50.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("x")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("z")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 20;
			LEVEL 0 FOR 25.0;
			LEVEL 1 FOR 25.0;
		}
	}
}

TRANSITION_LIST("x")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 41.2;
		LEVEL 1 FOR 43.2;
		LEVEL 0 FOR 82.08;
		LEVEL 1 FOR 66.88;
		LEVEL 0 FOR 68.88;
		LEVEL 1 FOR 45.2;
		LEVEL 0 FOR 117.6;
		LEVEL 1 FOR 44.8;
		LEVEL 0 FOR 75.76;
		LEVEL 1 FOR 97.6;
		LEVEL 0 FOR 80.0;
		LEVEL 1 FOR 25.6;
		LEVEL 0 FOR 211.2;
	}
}

TRANSITION_LIST("z")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 127.8;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 200.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 100.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 250.0;
		LEVEL 1 FOR 50.0;
		LEVEL 0 FOR 122.2;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "x";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "z";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 10300;
	MASTER = TRUE;
}
;