计数器：wait语句的应用.txt

来自「很好的VHDL源码,里面有不少实用的实例!」· 文本 代码 · 共 32 行

-- This example shows an inefficient way of describing a counter. 
-- vhdl model of a 3-state counter illustrating the use
-- of the WAIT statement to suspend a process.At each wait
-- statement the simulation time is updated one cycle,transferring 
-- the driver value to the output count.
-- This architecture shows that there is no difference between
-- WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'
-- dowload from: www.fpga.com.cn & www.pld.com.cn

library ieee;
use ieee.std_logic_1164.all;

ENTITY cntr3 IS
   PORT(clock : IN BIT; count : OUT NATURAL);
END cntr3;

ARCHITECTURE using_wait OF cntr3 IS
BEGIN
   PROCESS
   BEGIN
      --WAIT UNTIL (clock'EVENT AND clock = '1');
      WAIT UNTIL clock = '1';
      count <= 0;
      --WAIT UNTIL (clock'EVENT AND clock = '1');
      WAIT UNTIL clock = '1';
      count <= 1;
      --WAIT UNTIL (clock'EVENT AND clock = '1');
      WAIT UNTIL clock = '1'; 
      count <= 2;
   END PROCESS;
END using_wait;