📄 s3c4510.h
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#ifndef _S3C4510_H_#define _S3C4510_H_#include <asm/io.h>#define INB(a) inb(a)#define OUTB(a,d) outb(d,a)#define S3C4510_CHAIN_LENGTH 233#define UARXD1_IN 0#define nUADSR0_OUT 1#define UATXD0_OUT 2#define nUADTR0_IN 3#define UARXD0_IN 4#define SDA_OUT 5 // OPEN DRAIN OUTPUT#define SDA_IN 6#define SCL_OUT 7#define SCL_IN 8#define P17_ENB 9 // *#define P17_OUT 10#define P17_IN 11#define P16_ENB 12 // *#define P16_OUT 13#define P16_IN 14#define P15_ENB 15 // *#define P15_OUT 16#define P15_IN 17#define P14_ENB 18 // *#define P14_OUT 19#define P14_IN 20#define P13_ENB 21 // *#define P13_OUT 22#define P13_IN 23#define P12_ENB 24 // *#define P12_OUT 25#define P12_IN 26#define P11_ENB 27 // *#define P11_OUT 28#define P11_IN 29#define P10_ENB 30 // *#define P10_OUT 31#define P10_IN 32#define P9_ENB 33 // *#define P9_OUT 34#define P9_IN 35#define P8_ENB 36 // *#define P8_OUT 37#define P8_IN 38#define P7_ENB 39 // *#define P7_OUT 40#define P7_IN 41#define P6_ENB 42 // *#define P6_OUT 43#define P6_IN 44#define P5_ENB 45 // *#define P5_OUT 46#define P5_IN 47#define P4_ENB 48 // *#define P4_OUT 49#define P4_IN 50#define P3_ENB 51 // *#define P3_OUT 52#define P3_IN 53#define P2_ENB 54 // *#define P2_OUT 55#define P2_IN 56#define P1_ENB 57 // *#define P1_OUT 58#define P1_IN 59#define P0_ENB 60 // *#define P0_OUT 61#define P0_IN 62#define D31_OUT 63#define D31_IN 64#define D30_OUT 65#define D30_IN 66#define D29_OUT 67#define D29_IN 68#define D28_OUT 69#define D28_IN 70#define D27_OUT 71#define D27_IN 72#define D26_OUT 73#define D26_IN 74#define D25_OUT 75#define D25_IN 76#define D24_OUT 77#define D24_IN 78#define D23_OUT 79#define D23_IN 80#define D22_OUT 81#define D22_IN 82#define D21_OUT 83#define D21_IN 84#define D20_OUT 85#define D20_IN 86#define D19_OUT 87#define D19_IN 88#define D18_OUT 89#define D18_IN 90#define D17_OUT 91#define D17_IN 92#define D16_OUT 93#define D16_IN 94#define D15_OUT 95#define D15_IN 96#define D14_OUT 97#define D14_IN 98#define D13_OUT 99#define D13_IN 100#define D12_OUT 101#define D12_IN 102#define D11_OUT 103#define D11_IN 104#define D10_OUT 105#define D10_IN 106#define D9_OUT 107#define D9_IN 108#define D8_OUT 109#define D8_IN 110#define D7_OUT 111#define D7_IN 112#define D6_OUT 113#define D6_IN 114#define D5_OUT 115#define D5_IN 116#define D4_OUT 117#define D4_IN 118#define D3_OUT 119#define D3_IN 120#define D2_OUT 121#define D2_IN 122#define D1_OUT 123#define D1_IN 124#define D0_OUT 125#define D0_IN 126#define D_OUT_ENB 127 // *#define A21_OUT 128#define A20_OUT 129#define A19_OUT 130#define A18_OUT 131#define A17_OUT 132#define A16_OUT 133#define A15_OUT 134#define A14_OUT 135#define A13_OUT 136#define A12_OUT 137#define A11_OUT 138#define A10_OUT 139#define A9_OUT 140#define A8_OUT 141#define A7_OUT 142#define A6_OUT 143#define A5_OUT 144#define A4_OUT 145#define A3_OUT 146#define A2_OUT 147#define A1_OUT 148#define A0_OUT 149#define ExtMACK_OUT 150#define ExtMREQ_IN 151#define nWBE_3_OUT 152#define nWBE_2_OUT 153#define nWBE_1_OUT 154#define nWBE_0_OUT 155#define nDWE_OUT 156#define nCAS_3_OUT 157#define nCAS_2_OUT 158#define nCAS_1_OUT 159#define nCAS_0_OUT 160#define nRAS_3_OUT 161#define nRAS_2_OUT 162#define nRAS_1_OUT 163#define nRAS_0_OUT 164#define nRCS_5_OUT 165#define nRCS_4_OUT 166#define nRCS_3_OUT 167#define nRCS_2_OUT 168#define nRCS_1_OUT 169#define CLKSEL_IN 170#define nRESET_IN 171#define MCLK_IN 172#define MCLKO_OUT 173#define CLKOEN_IN 174#define nRCS_0_OUT 175#define B0SIZE_1_IN 176#define B0SIZE_0_IN 177#define nOE_OUT 178#define nEWAIT_IN 179#define nECS_3_OUT 180#define nECS_2_OUT 181#define nECS_1_OUT 182#define nECS_0_OUT 183#define DIS_BUS 184 // *#define UCLK_IN 185#define TMODE_IN 186#define MDC_OUT 187#define LITTLE_IN 188#define MDIO_OE 189#define MDIO_OUT 190#define MDIO_IN 191#define TX_EN_TXEN_10M_OUT 192#define TX_CLK_TXCLK_10M_OUT 193#define TX_ERR_PCOMP_10M_OUT 194#define TXD3_OUT 195#define TXD2_OUT 196#define TXD1_LOOP10_OUT 197#define TXD0_TXD_10M_OUT 198#define COL_COL_10M_IN 199#define RX_CLK_RXCLK_10M_IN 200#define RX_ERR_IN 201#define RXD3_IN 202#define RXD2_IN 203#define RXD1_IN 204#define RXD0_RXD_10M_IN 205#define RX_DV_LINK10_IN 206#define CRS_CRS_10M_IN 207#define TXCBEN 208 // *#define TXCB_OUT 209#define TXCB_IN 210#define nSYNCB_OUT 211#define RXCB_IN 212#define nDCDB_IN 213#define nCTSB_IN 214#define TXDB_OUT 215#define nRTSB_OUT 216#define RXDB_IN 217#define nDTRB_OUT 218#define TXCAEN 219 // *#define TXCA_OUT 220#define TXCA_IN 221#define nSYNCA_OUT 222#define RXCA_IN 223#define nDCDA_IN 224#define nCTSA_IN 225#define TXDA_OUT 226#define nRTSA_OUT 227#define RXDA_IN 228#define nDTRA_OUT 229#define nUADSR1_OUT 230#define UATXD1_OUT 231#define nUADTR1_IN 232#define TRST 0x01#define LPT1 0x3bc // hardware base address for parallel port#define LPT2 0x378 // the search order is LPT1 then 2 then 3#define LPT3 0x278 // first valid address found is used (re-order if needed for multiple ports)#define READ 0 // Flags used to modify the S3C4510 JTAG chain data depending on#define WRITE 1 // the access mode of the Flash Memory#define SETUP 2#define HOLD 3#define RS 4#define NONE 5#define IP 0 // Flag used when accessing the parallel port#define RP 1 // RP = 'read port', IP = 'ignore port', using IP will speed access#define S3C4510ID "**** 1111000011110000 11110000111 1" // JTAG ID-codes for the S3C4510 // "0001 1111000011110000 11110000111 1"//function declareint io_access_on( unsigned int port );void io_access_off( unsigned int port );int test_port( void );int putp( int tdi, int tms, int rp );void reset_jtag( void );void test_logic_reset( void );int check_id( char *device_id );int id_command( void );void bypass_all( void );void extest( void );unsigned int access_bus( int rw, unsigned int address, unsigned int data, int rp);#endif //#ifndef _S3C4510_H_
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