📄 post.h
字号:
PrintSerial(pstring, 0);
sprintf(pstring, "\n");
PrintSerial(pstring, 0);
}
}
__inline void DM_ControlWordsDebugPrintPutBit(int controlWord, int flag)
{
}
__inline void DM_StartTest(char* test)
{
}
__inline int DM_StopTest(char* s)
{
return (1);
}
__inline void DM_FinishTest(char* test)
{
}
__inline void DM_Printf(char* fmt, ...)
{
}
__inline void DM_Message(char* msg)
{
}
__inline void DM_Status(char* msg)
{
}
__inline int DM_GetKey(void)
{
return (0);
}
__inline char* GetNeponsetWhoAmI()
{
if (expansionBoardPresent())
{
return "Expansion board";
}
else
{
return "No Expansion board";
}
}
__inline char* XsClockRateString()
{
switch (GetCCCR())
{
case CORE_CLK_195_195_MHZ: // Run Mode: 195 MHZ, Turbo Mode: 195 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "195 MHZ - Turbo Mode";
}
else
{
return "195 MHZ - Run Mode";
}
case CORE_CLK_195_487_MHZ: // Run Mode: 195 MHZ, Turbo Mode: 487 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "487 MHZ - Turbo Mode";
}
else
{
return "195 MHZ - Run Mode";
}
case CORE_CLK_208_208_MHZ: // Run Mode: 208 MHZ, Turbo Mode: 208 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "208 MHZ - Turbo Mode";
}
else
{
return "208 MHZ - Run Mode";
}
case CORE_CLK_208_520_MHZ: // Run Mode: 208 MHZ, Turbo Mode: 520 MHZ
if (GetCCLKCFG() & CCLKCFG_TURBO)
{
return "520 MHZ - Turbo Mode";
}
else
{
return "208 MHZ - Run Mode";
}
}
return "";
}
__inline char* XsMemoryRateString()
{
int hwConfig = GetHWConfig();
if (hwConfig & HWConfig_BusSPEED)
{
return "50 MHZ";
}
else
{
return "100 MHZ";
}
}
__inline char* GetCpuTrademark()
{
int CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_TRADEMARK(CpuVersion))
{
case 0x69:
return "Intel Corporation";
default:
return "";
}
}
__inline char* GetCpuArchitecture()
{
int CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_ARCH_VER(CpuVersion))
{
case 0x05:
return "ARM Architecture version 5TE";
default:
return "";
}
}
__inline char* GetCpuCoreGeneration()
{
int CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_CORE_GEN(CpuVersion))
{
case 0x01:
return "Intel(T) XScale(TM) Microarchitecture";
default:
return "";
}
}
__inline char* GetCpuCoreRevision()
{
int CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_CORE_REV(CpuVersion))
{
case 0x0: // A0,A1
case 0x2: // B0,B1,B2,C0
return "First version";
default:
return "";
}
}
__inline char* GetCpuProductNumber(int flag)
{
int CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_PRODUCT_NUM(CpuVersion))
{
case 0x11: // PXA270
return "PXA270 Application Processor";
default:
return "";
}
}
__inline char* GetCpuProductRevision(int flag)
{
int CpuVersion = 0;
// Retrieve the CPU version information
CpuVersion = GetCpuVersion();
switch (CPU_PRODUCT_REV(CpuVersion))
{
case STEP_A0:
if (flag)
{
return "A0 Stepping";
}
else
{
return "A0";
}
case STEP_A1:
if (flag)
{
return "A1 Stepping";
}
else
{
return "A1";
}
case STEP_B0:
if (flag)
{
return "B0 Stepping";
}
else
{
return "B0";
}
case STEP_C0:
if (flag)
{
return "C0 Stepping";
}
else
{
return "C0";
}
default:
return "";
}
}
__inline char* GetMMUConfiguration()
{
if (IsMMUEnabled())
{
if (IsICacheEnabled())
{
if (IsDCacheEnabled())
{
return "MMU, ICache, DCache on";
}
else
{
return "MMU, ICache on";
}
}
else
{
return "MMU on";
}
}
else
{
return "MMU off";
}
}
// Allocate a memory block from the cached heap.
/*__inline void* malloc(int size)
{
return ((void*)0xA0400000);
}*/
// Allocate a memory block from the cached heap.
__inline int mallocx(int size, void **virtualAddr, void **physicalAddr)
{
return (0);
}
__inline void free(void* virtualAddr)
{
}
__inline int freex(void* virtualAddr)
{
return (0);
}
#endif // _post_h_
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