post.h

ARM9WindowsOS下电机控制 蜂鸣控制 需要高度自治的试验平台

/******************************************************************************
**
**  COPYRIGHT (C) 2000, 2001 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       post.h
**
**  PURPOSE:        This file contains the Power-On Self Test definitions for

**
**  LAST MODIFIED:  $Modtime: 5/15/02 3:35p $
******************************************************************************/

#ifndef _post_h_
#define _post_h_

#include <stdio.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
/*#include "memory.h"
#include "timers.h"
#include "registers.h"
#include "misc.h"
#include "intelFlash.h"
#include "FlashAPI.h"
#include "lan91C111.h"
#include "NetworkAPI.h"*/
#include "uarts.h"
#include "audio.h"
//#include "xsdma.h"
//#include "dc2003.h"

/*
*******************************************************************************
*
* POST Configuration Definitions
*
* Note:
*    The definitions below apply only to "C" language code. When modifying
*    these definitions, make the corresponding change to POSTSTARTUP.INC for
*    the assembly langue code. The assembly language header file is NOT common
*    with the "C" header file.
*
*******************************************************************************
*/

//
// The definitions below apply only to "C" code. When modifying these
// definitions, make the corresponding change to poststartup.inc for 
// assembly code. The assembly language header file is NOT common with the
// "C" header file. The POST version information is defined in version.inc.
//
// Bits 31:28 - Major, 27:24 Minor 23:19 Edit
#define POST_MAJOR_VERSION_MASK   0xF0000000    // Major version
#define POST_MINOR_VERSION_MASK   0x0F000000    // Minor version
#define POST_EDIT_VERSION_MASK    0x00F00000    // Edit version

// Test configuration bit definitions.
#define TEST_REGISTERS    0x00000001    // Bit 0 - Register test
#define TEST_SDRAM        0x00000002    // Bit 1 - SDRAM test
#define TEST_SRAM         0x00000004    // Bit 2 - SRAM test
#define TEST_DISCRETE_LED 0x00000008    // Bit 3 - Discrete LEDs test
#define TEST_USER_SW      0x00000010    // Bit 4 - User Switches test
#define TEST_FLASH        0x00000020    // Bit 5 - Flash test
#define TEST_ETHERNET     0x00000040    // Bit 6 - Ethernet test
#define TEST_UARTS        0x00000080    // Bit 7 - UART test
#define TEST_AC97         0x00000100    // Bit 8 - AC97 test
#define TEST_LCD          0x00000200    // Bit 9 - LCD test
#define TEST_I2C          0x00000400    // Bit 10 - I2C test
#define TEST_DC           0x00000800    // Bit 11 - DC2003 test
#define TEST_MEMSTICK	  0x00001000	// Bit 12 - MemoryStick test
#define TEST_IRDA	 	  0x00002000	// Bit 13 - IRDA test
#define TEST_PI2C         0x00004000    // Bit 15 - PMIC test


// Process Status word definitions.
#define CPSR_I_Bit        0x80          // Processor IRQ disable bit
#define CPSR_F_Bit        0x40          // Processor Fast IRQ disable bit

/*
************************************************************************************
*    Assembly Language Hardware Configuraiton
*
*    Note:
*        These definitions can be used to test the state of the value
*        returned from either GetSCR or GetHWConfig.
*
************************************************************************************
*/
#define HWConfig_RESET      (0x1U << 0)
#define HWConfig_PORT       (0x1U << 1)
#define HWConfig_FIFO       (0x1U << 2)
#define HWConfig_EX_BOARD   (0x1U << 3)
#define HWConfig_LCD        (0x1U << 4)
#define HWConfig_EXPN       (0x1U << 5)
#define HWConfig_DbgMODE    (0x1U << 6)
#define HWConfig_PLL        (0x1U << 7)
#define HWConfig_STEPPING   (0xFU << 8)
#define HWConfig_BootromPM  (0x1U << 12)
#define HWConfig_AppflashPM (0x1U << 16)
#define HWConfig_PAGEMODE   (HWConfig_BootromPM + HWConfig_AppflashPM)
#define HWConfig_BOOTROM    (0xFU << 12)
#define HWConfig_APPFLASH   (0xFU << 16)
#define HWConfig_BusWIDTH01 (0x1U << 20)
#define HWConfig_SPEED01    (0x1U << 21)
#define HWConfig_SDRAM0     (0x1U << 22)
#define HWConfig_SDRAM1     (0x1U << 23)
#define HWConfig_BusWIDTH23 (0x1U << 24)
#define HWConfig_SPEED23    (0x1U << 25)
#define HWConfig_SDRAM2     (0x1U << 26)
#define HWConfig_SDRAM3     (0x1U << 27)
#define HWConfig_BusWIDTH   (HWConfig_BusWIDTH01 + HWConfig_BusWIDTH23)
#define HWConfig_BusSPEED   (HWConfig_SPEED01 + HWConfig_SPEED23)
#define HWConfig_HWR        (0x1U << 28)
#define HWConfig_WDR        (0x1U << 29)
#define HWConfig_SMR        (0x1U << 30)
#define HWConfig_GPR        (0x1U << 31)

// Processor ID definitions in the form:
// Bits 31:24 - Implementation Trademark - 0x69
//      23:16 - Architecture Version - 0x05
//      15:13 - Core Generation - 0b001 - Intel(r) XScale(tm) Core
//      12:10 - Core Revision - 0b000 - First version of the core
//                              0b010 - Core version for B0/B1
//       9:4  - Product Number - 0b010001 - PXA270 Application Processor
//       3:0  - Product Revision - 0b0000 - A0 Stepping
//                                 0b0001 - A1 Stepping
//                                 0b0002 - B0 Stepping
//                                 0b0003 - B1 Stepping
//                                 0b0004 - C0 Stepping
//
//                   33222222 22221111 111 111 000000 0000
//                   10987654 32109876 543 210 987654 3210
//                   -------- -------- --- --- ------ ----
// 0x69052100 - A0 - 01101001 00000101 001 000 010000 0000 - PXA250
// 0x69052101 - A1 - 01101001 00000101 001 000 010000 0001 - PXA250
// 0x69052902 - B0 - 01101001 00000101 001 010 010000 0010 - PXA250
// 0x69052903 - B1 - 01101001 00000101 001 010 010000 0011 - PXA250
// 0x69052904 - B2 - 01101001 00000101 001 010 010000 0100 - PXA250
// 0x69052D05 - C0 - 01101001 00000101 001 011 010000 0101 - PXA250
//
// 0x69052122 - A1 - 01101001 00000101 001 000 010010 0010 - PXA210
// 0x69052923 - B1 - 01101001 00000101 001 010 010010 0011 - PXA210
// 0x69052924 - B2 - 01101001 00000101 001 010 010010 0101 - PXA210
// 0x69052D25 - C0 - 01101001 00000101 001 011 010010 0101 - PXA210

// 0x69054111 - A1 - 01101001 00000101 010 000 010001 0001 - PXA270
// 0x69054112 - B0 - 01101001 00000101 010 000 010001 0010 - PXA270
// 0x69054112 - C0 - 01101001 00000101 010 000 010001 0100 - PXA270

#define CPU_TRADEMARK_MASK     (0xFFU << 24)    // 0x69 = Intel(r) Corporation
#define CPU_ARCH_VER_MASK      (0xFFU << 16)    // 0x05 ARM V5
#define CPU_CORE_GEN_MASK      (0x07U << 13)    // 0x1 - Intel XScale
#define CPU_CORE_REV_MASK      (0x07U << 10)    // 0x0 - First version
#define CPU_PRODUCT_NUM_MASK   (0x3FU << 4)     // 0x10 - PXA250
#define CPU_PRODUCT_REV_MASK   (0x0FU << 0)     // 0x0 - Stepping

// Processor ID macros
#define CPU_TRADEMARK(x)   ((x & CPU_TRADEMARK_MASK)   >> 24)
#define CPU_ARCH_VER(x)    ((x & CPU_ARCH_VER_MASK)    >> 16)
#define CPU_CORE_GEN(x)    ((x & CPU_CORE_GEN_MASK)    >> 13)
#define CPU_CORE_REV(x)    ((x & CPU_CORE_REV_MASK)    >> 10)
#define CPU_PRODUCT_NUM(x) ((x & CPU_PRODUCT_NUM_MASK) >> 4)
#define CPU_PRODUCT_REV(x) ((x & CPU_PRODUCT_REV_MASK) >> 0)

// Stepping definitions.
#define STEP_A0    0x00
#define STEP_A1    0x01
#define STEP_B0    0x02
#define STEP_B1    0x03
#define STEP_C0    0x04

// Core clock definitions
// Run Mode: 195 MHZ, Turbo Mode: 195 MHZ
#define CORE_CLK_195_195_MHZ    0x10F
// Run Mode: 195 MHZ, Turbo Mode: 487 MHZ
#define CORE_CLK_195_487_MHZ    0x28F
// Run Mode: 208 MHZ, Turbo Mode: 208 MHZ
#define CORE_CLK_208_208_MHZ    0x110
// Run Mode: 208 MHZ, Turbo Mode: 520 MHZ
#define CORE_CLK_208_520_MHZ    0x290

// Core Clock Configuration Register definitions.
#define CCLKCFG_TURBO (0x1U << 0)
#define CCLKCFG_FCS   (0x1U << 1)
#define CCLKCFG_FAST  (0x1U << 3)

// Common definitions
//#define DM_WaitMs WaitMs
//#define DM_WaitUs WaitUs
void WaitMs(int msVal);
/*
************************************************************************************
*    Assembly Language Function Prototypes 
************************************************************************************
*/

int GetSCR(void);
int SetBCR(int BCR);
int GetBCR(void);
int GetTestConfig(void);
int GetCpuVersion(void);
int VirtualToPhysical(void* vaP, void* paP);
int PhysicalToVirtual(void* paP, int flag, void* vaP);
int IsMMUEnabled(void);
int IsICacheEnabled(void);
int IsDCacheEnabled(void);
int GetPostVersion(void);
int GetHWConfig(void);
int GetCCCR(void);
int GetCCLKCFG(void);
int GetSW(void);
int GetSW4(void);
int GetDIP(void);
int GetID(void);



// External references.
extern int PrintFlag;
extern int SerialPort;


__inline void POST_SerialPrintf(char* fmt, ...)
{
    char pstring[100];
    va_list ap;
     void* p1, *p2, *p3, *p4, *p5, *p6, *p7, *p8, *p9, *p10, *p11, *p12;

    if (PrintFlag)
    {
        sprintf(pstring, "\n");
        PrintSerial(pstring, 0);

        va_start(ap, fmt);
        p1 = va_arg(ap, void*);
        p2 = va_arg(ap, void*);
        p3 = va_arg(ap, void*);
        p4 = va_arg(ap, void*);
        p5 = va_arg(ap, void*);
        p6 = va_arg(ap, void*);
        p7 = va_arg(ap, void*);
        p8 = va_arg(ap, void*);
        p9 = va_arg(ap, void*);
        p10 = va_arg(ap, void*);
        p11 = va_arg(ap, void*);
        p12 = va_arg(ap, void*);
        va_end(ap);

        sprintf(pstring, fmt, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12);
        PrintSerial(pstring, 0);

        sprintf(pstring, "\n");
        PrintSerial(pstring, 0);
    }
}

__inline void DM_DbgPrintf(char* fmt, ...)
{
    char pstring[100];
    va_list ap;
     void* p1, *p2, *p3, *p4, *p5, *p6, *p7, *p8, *p9, *p10, *p11, *p12;

    if (PrintFlag)
    {
        sprintf(pstring, "\n");
        PrintSerial(pstring, 0);

        va_start(ap, fmt);
        p1 = va_arg(ap, void*);
        p2 = va_arg(ap, void*);
        p3 = va_arg(ap, void*);
        p4 = va_arg(ap, void*);
        p5 = va_arg(ap, void*);
        p6 = va_arg(ap, void*);
        p7 = va_arg(ap, void*);
        p8 = va_arg(ap, void*);
        p9 = va_arg(ap, void*);
        p10 = va_arg(ap, void*);
        p11 = va_arg(ap, void*);
        p12 = va_arg(ap, void*);
        va_end(ap);

        sprintf(pstring, fmt, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12);