📄 mcu.h
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/* PORTG : Data Register, Port G */
#define PORTG4 4
#define PORTG3 3
#define PORTG2 2
#define PORTG1 1
#define PORTG0 0
/* TFR0 : Timer/Counter Interrupt Flag Register 0 */
#define OCF0A 1
#define TOV0 0
/* TFR1 : Timer/Counter Interrupt Flag Register 1 */
#define ICF1 5
#define OCF1C 3
#define OCF1B 2
#define OCF1A 1
#define TOV1 0
/* TFR2 : Timer/Counter Interrupt Flag Register 2 */
#define OCF2A 1
#define TOV2 0
/* TFR3 : Timer/Counter Interrupt Flag Register 3 */
#define ICF3 5
#define OCF3C 3
#define OCF3B 2
#define OCF3A 1
#define TOV3 0
/* EIFR : External Interrupt Flag Register */
#define INTF7 7
#define INTF6 6
#define INTF5 5
#define INTF4 4
#define INTF3 3
#define INTF2 2
#define INTF1 1
#define INTF0 0
/* EIMSK : External Interrupt Mask Register */
#define INT7 7
#define INT6 6
#define INT5 5
#define INT4 4
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* EECR : EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* GTCCR : General Timer Control Register */
#define TSM 7
#define PSR2 1
#define PSR310 0
/* TCCR0A : Timer/Counter 0 Control Register */
#define FOC0A 7
#define WGM00 6
#define COM0A1 5
#define COM0A0 4
#define WGM01 3
#define CS02 2
#define CS01 1
#define CS00 0
/* SPCR : SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* SPSR : SPI Status Register */
#define SPIF 7
#define WCOL 6
#define SPI2X 0
/* ACSR : Analog Comparator Control and Status Register */
#define ACD 7
#define ACBG 6
#define ACO 5
#define ACI 4
#define ACIE 3
#define ACIC 2
#define ACIS1 1
#define ACIS0 0
/* OCDR : On-Chip Debug Register */
#define IDRD 7
#define OCDR7 7
#define OCDR6 6
#define OCDR5 5
#define OCDR4 4
#define OCDR3 3
#define OCDR2 2
#define OCDR1 1
#define OCDR0 0
/* SMCR : Sleep Mode Control Register */
#define SM2 3
#define SM1 2
#define SM0 1
#define SE 0
/* MCUSR : MCU general Status Register */
#define JTRF 4
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* MCUCR : MCU general Control Register */
#define JTD 7
#define PUD 4
#define IVSEL 1
#define IVCE 0
/* SPMCR : Store Program Memory Control and Status Register */
#define SPMIE 7
#define RWWSB 6
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* RAMPZ : RAM Page Z Select Register */
#define RAMPZ0 0
/* SPH : Stack Pointer High */
#define SP15 7
#define SP14 6
#define SP13 5
#define SP12 4
#define SP11 3
#define SP10 2
#define SP9 1
#define SP8 0
/* SPL : Stack Pointer Low */
#define SP7 7
#define SP6 6
#define SP5 5
#define SP4 4
#define SP3 3
#define SP2 2
#define SP1 1
#define SP0 0
/* WTDCR : Watchdog Timer Control Register */
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* CLKPR : Source Clock Prescaler Register */
#define CKLPCE 7
#define CKLPS3 3
#define CKLPS2 2
#define CKLPS1 1
#define CKLPS0 0
/* TIMSK0 : Timer Interrupt Mask Register0 */
#define OCIE0A 1
#define TOIE0 0
/* TIMSK1 : Timer Interrupt Mask Register1 */
#define ICIE1 5
#define OCIE1C 3
#define OCIE1B 2
#define OCIE1A 1
#define TOIE1 0
/* TIMSK2 : Timer Interrupt Mask Register2 */
#define OCIE2A 1
#define TOIE2 0
/* TIMSK3 : Timer Interrupt Mask Register3 */
#define ICIE3 5
#define OCIE3C 3
#define OCIE3B 2
#define OCIE3A 1
#define TOIE3 0
/* XMCRA : External Memory Control A Register */
#define SRE 7
#define SRL2 6
#define SRL1 5
#define SRL0 4
#define SRW11 3
#define SRW10 2
#define SRW01 1
#define SRW00 0
/* XMCRB : External Memory Control B Register */
#define XMBK 7
#define XMM2 2
#define XMM1 1
#define XMM0 0
/* ADCSRA : ADC Control and Status Register A*/
#define ADEN 7
#define ADSC 6
#define ADRF 5
#define ADIF 4
#define ADIE 3
#define ADPS2 2
#define ADPS1 1
#define ADPS0 0
/* ADCSRB : ADC Control and Status Register B*/
#define ADCHSM 7
#define ACME 6
#define ADST2 2
#define ADST1 1
#define ADST0 0
/* ADMUX : ADC Multiplexer Selection Register */
#define REFS1 7
#define REFS0 6
#define ADLAR 5
#define MUX4 4
#define MUX3 3
#define MUX2 2
#define MUX1 1
#define MUX0 0
/* TCCR1A : Timer/Counter 1 Control Register A */
#define COM1A1 7
#define COM1A0 6
#define COM1B1 5
#define COM1B0 4
#define COM1C1 3
#define COM1C0 2
#define WGM11 1
#define WGM10 0
/* TCCR1B : Timer/Counter 1 Control Register B */
#define ICNC1 7
#define ICES1 6
#define WGM13 4
#define WGM12 3
#define CS12 2
#define CS11 1
#define CS10 0
/* TCCR1C : Timer/Counter 1 Control Register C */
#define FOC1A 7
#define FOC1B 6
#define FOC1C 5
/* TCCR3A : Timer/Counter 3 Control Register A */
#define COM3A1 7
#define COM3A0 6
#define COM3B1 5
#define COM3B0 4
#define COM3C1 3
#define COM3C0 2
#define WGM31 1
#define WGM30 0
/* TCCR3B : Timer/Counter 3 Control Register B */
#define ICNC3 7
#define ICES3 6
#define WGM33 4
#define WGM32 3
#define CS32 2
#define CS31 1
#define CS30 0
/* TCCR3C : Timer/Counter 3 Control Register C */
#define FOC3A 7
#define FOC3B 6
#define FOC3C 5
/* TCCR2A : Timer/Counter 2 Control Register A*/
#define FOC2 7
#define WGM20 6
#define COM21 5
#define COM20 4
#define WGM21 3
#define CS22 2
#define CS21 1
#define CS20 0
/* ASSR : Asynchronous mode Status Register */
#define EXCLK 4
#define AS2 3
#define TCN2UB 2
#define OCR2UB 1
#define TCR2UB 0
/* TWSR : TWI Status Register */
#define TWS7 7
#define TWS6 6
#define TWS5 5
#define TWS4 4
#define TWS3 3
#define TWPS1 1
#define TWPS0 0
/* TWAR : TWI (slave) Address Register */
#define TWA6 7
#define TWA5 6
#define TWA4 5
#define TWA3 4
#define TWA2 3
#define TWA1 2
#define TWA0 1
#define TWGCE 0
/* TWCR : TWI Control Register */
#define TWINT 7
#define TWEA 6
#define TWSTA 5
#define TWSTO 4
#define TWWC 3
#define TWEN 2
#define TWIE 0
/* UCSR0A : USART0 Control and Status Register A */
#define RXC0 7
#define TXC0 6
#define UDRE0 5
#define FE0 4
#define DOR0 3
#define UPE0 2
#define U2X0 1
#define MPCM0 0
/* UCSR0B : USART0 Control and Status Register B */
#define RXCIE0 7
#define TXCIE0 6
#define UDRIE0 5
#define RXEN0 4
#define TXEN0 3
#define UCSZ02 2
#define RXB80 1
#define TXB80 0
/* UCSR0C : USART0 Control and Status Register C */
#define UMSEL0 6
#define UPM01 5
#define UPM00 4
#define USBS0 3
#define UCSZ01 2
#define UCSZ00 1
#define UCPOL0 0
/* UCSR1A : USART1 Control and Status Register A */
#define RXC1 7
#define TXC1 6
#define UDRE1 5
#define FE1 4
#define DOR1 3
#define UPE1 2
#define U2X1 1
#define MPCM1 0
/* UCSR1B : USART1 Control and Status Register B */
#define RXCIE1 7
#define TXCIE1 6
#define UDRIE1 5
#define RXEN1 4
#define TXEN1 3
#define UCSZ12 2
#define RXB81 1
#define TXB81 0
/* UCSR1C : USART1 Control and Status Register C */
#define UMSEL1 6
#define UPM11 5
#define UPM10 4
#define USBS1 3
#define UCSZ11 2
#define UCSZ10 1
#define UCPOL1 0
/* CANGCON : CAN General Control Register */
#define ABRQ 7
#define OVRQ 6
#define TTC 5
#define SYNCTTC 4
#define LISTEN 3
#define ENA 1
#define SWRES 0
/* CANGSTA : CAN General Status Register */
#define OVFG 6
#define TXBSY 4
#define RXBSY 3
#define ENFG 2
#define BOFF 1
#define ERRP 0
/* CANGIT : CAN General Interrupt Register */
#define CANIT 7
#define BOFFIT 6
#define OVRTIM 5
#define OVRBUF 4
#define SERG 3
#define CERG 2
#define FERG 1
#define AERG 0
#define ERR_GEN_msk 0x0F
#define INT_GEN_msk 0x5F
/* CANGIE : CAN General Interrupt Enable Register */
#define ENIT 7
#define ENBOFF 6
#define ENRX 5
#define ENTX 4
#define ENERMOB 3
#define ENBUF 2
#define ENERG 1
#define ENOVRT 0
/* CANBT1: CAN Bit Timing 1 Register */
#define BRP 1
#define BRP_msk 0x7E
/* CANBT2: CAN Bit Timing 2 Register */
#define SJW 5
#define SJW_msk 0x60
#define PRS 1
#define PRS_msk 0x0E
/* CANBT3: CAN Bit Timing 3 Register */
#define PHS2 4
#define PHS2_msk 0x70
#define PHS1 1
#define PHS1_msk 0x0E
#define SMP 0
/* CANHPMOB : CAN Highest Priority MOB Register */
#define HPMOB 4
#define HPMOB_msk 0xF0
/* CANPAGE : CAN MOB Page Register */
#define AINC 3
#define MOBNB 4
#define MOBNB_msk 0xF0
/* CANSTMOB : CAN MOB Status Register */
#define DLCW 7
#define TXOK 6
#define RXOK 5
#define BERR 4
#define SERR 3
#define CERR 2
#define FERR 1
#define AERR 0
#define ERR_MOB_msk 0x1F
#define INT_MOB_msk 0x7F
/* CANCDMOB : CAN MOB Control Register */
#define CONMOB 6
#define CONMOB_msk 0xC0
#define RPLY 5
#define IDE 4
#define DLC 0
#define DLC_msk 0x0F
/* CANIDT4 : CAN Identifier Tag 4 Register */
#define RTRTAG 2
#define RB1TAG 1
#define RB0TAG 0
/* CANIDM4 : CAN Identifier Mask 4 Register */
#define RTRMSK 2
#define IDEMSK 0
/* Pointer definition */
#define XL r26
#define XH r27
#define YL r28
#define YH r29
#define ZL r30
#define ZH r31
#endif /* _MCU_H*/
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