uart_regs.v

uart16550 ＩＰ核 ＨＤＬ源代码

begin
	if (wb_rst_i)
		msi_reset <= #1 0;
	else
	if (msi_reset)
		msi_reset <= #1 0;
	else
	if (wb_re_i && wb_addr_i == `UART_REG_MS)
		msi_reset <= #1 1; // reset bits in Modem Status Register
end

// threi_clear signal handling
always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		threi_clear <= #1 0;
	else
	if (threi_clear && !lsr[`UART_LS_TFE] && (tf_count==0)) // reset clear flag when tx fifo clears
		threi_clear <= #1 0;
	else
	if (wb_re_i && wb_addr_i == `UART_REG_II)
		threi_clear <= #1 1; // reset bits in Modem Status Register
end

//
//   WRITES AND RESETS   //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		lcr <= #1 8'b00000011; // 8n1 setting
	else
	if (wb_we_i && wb_addr_i==`UART_REG_LC)
		lcr <= #1 wb_dat_i;

// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
	begin
		ier <= #1 4'b0000; // no interrupts after reset
		dl[`UART_DL2] <= #1 8'b0;
	end
	else
	if (wb_we_i && wb_addr_i==`UART_REG_IE)
		if (dlab)
		begin
			dl[`UART_DL2] <= #1 wb_dat_i;
		end
		else
			ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb


// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i) begin
		fcr <= #1 2'b11; 
		rx_reset <= #1 0;
		tx_reset <= #1 0;
	end else
	if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
		fcr <= #1 wb_dat_i[7:6];
		rx_reset <= #1 wb_dat_i[1];
		tx_reset <= #1 wb_dat_i[2];
	end else begin // clear rx_reset, tx_reset signals when not written to
		rx_reset <= #1 0;
		tx_reset <= #1 0;
	end

// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		mcr <= #1 5'b0; 
	else
	if (wb_we_i && wb_addr_i==`UART_REG_MC)
			mcr <= #1 wb_dat_i[4:0];

// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
	begin
		dl[`UART_DL1]  <= #1 8'b0;
		tf_push   <= #1 1'b0;
		start_dlc <= #1 1'b0;
	end
	else
	if (wb_we_i && wb_addr_i==`UART_REG_TR)
		if (dlab)
		begin
			dl[`UART_DL1] <= #1 wb_dat_i;
			start_dlc <= #1 1'b1; // enable DL counter
			tf_push <= #1 1'b0;
		end
		else
		begin
			tf_push   <= #1 1'b1;
			start_dlc <= #1 1'b0;
		end
	else
	begin
		start_dlc <= #1 1'b0;
		tf_push   <= #1 1'b0;
	end

// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr[`UART_FC_TL])
	case (fcr[`UART_FC_TL])
		2'b00 : trigger_level = 1;
		2'b01 : trigger_level = 4;
		2'b10 : trigger_level = 8;
		2'b11 : trigger_level = 14;
	endcase
	
//
//  STATUS REGISTERS  //
//

// Modem Status Register
always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		msr <= #1 0;
	else begin
		msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
			msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
		msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
	end
end

// Line Status Register
always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		lsr <= #1 8'b01100000;
	else
	if (lsr_mask)
		lsr <= #1 lsr & 8'b00000001;
	else
	begin
		lsr[0] <= #1 (rf_count!=4'b0);  // data in receiver fifo available
		lsr[1] <= #1 rf_overrun;     // Receiver overrun error
		lsr[2] <= #1 rf_data_out[1]; // parity error bit
		lsr[3] <= #1 rf_data_out[0]; // framing error bit
		lsr[4] <= #1 (counter_b==4'b0); // break counter reached 0
		lsr[5] <= #1 (tf_count==5'b0);  // transmitter fifo is empty
		lsr[6] <= #1 (tf_count==5'b0 && (state == /*`S_IDLE */ 0)); // transmitter empty
		lsr[7] <= #1 rf_error_bit;
	end
end

// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		dlc    <= #1 0;
		enable <= #1 1'b0;
	end
	else
	begin
		if (start_dlc)
		begin
			enable <= #1 1'b0;
			dlc    <= #1 dl;
		end
		else
		begin
			if (dl!=0)
			begin
				if ( (dlc-1)==0 )
				begin
					enable <= #1 1'b1;
					dlc <= #1 dl;
				end
				else
				begin
					enable <= #1 1'b0;
					dlc <= #1 dlc - 1;
				end
			end
			else
			begin
				dlc <= #1 0;
				enable <= #1 1'b0;
			end
		end
	end
end

//
//	INTERRUPT LOGIC
//
always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		rls_int  <= #1 1'b0;
		rda_int  <= #1 1'b0;
		ti_int   <= #1 1'b0;
		thre_int <= #1 1'b0;
		ms_int   <= #1 1'b0;
	end
	else
	begin
		rls_int  <= #1 ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
		rda_int  <= #1 ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
		thre_int <= #1 threi_clear ? 0 : ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
		ms_int   <= #1 ier[`UART_IE_MS] && (| msr[3:0]);
		ti_int   <= #1 ier[`UART_IE_RDA] && (counter_t == 6'b0);
	end
end

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)	
		int_o <= #1 1'b0;
	else
		if (| {rls_int,rda_int,thre_int,ms_int,ti_int})
			int_o <= #1 1'b1;
		else
			int_o <= #1 1'b0;
end


// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		iir <= #1 1;
	else
	if (rls_int)  // interrupt occured and is enabled  (not masked)
	begin
		iir[`UART_II_II] <= #1 `UART_II_RLS;	// set identification register to correct value
		iir[`UART_II_IP] <= #1 1'b0;		// and clear the IIR bit 0 (interrupt pending)
	end
	else
	if (rda_int)
	begin
		iir[`UART_II_II] <= #1 `UART_II_RDA;
		iir[`UART_II_IP] <= #1 1'b0;
	end
	else
	if (ti_int)
	begin
		iir[`UART_II_II] <= #1 `UART_II_TI;
		iir[`UART_II_IP] <= #1 1'b0;
	end
	else
	if (thre_int)
	begin
		iir[`UART_II_II] <= #1 `UART_II_THRE;
		iir[`UART_II_IP] <= #1 1'b0;
	end
	else
	if (ms_int)
	begin
		iir[`UART_II_II] <= #1 `UART_II_MS;
		iir[`UART_II_IP] <= #1 1'b0;
	end
	else	// no interrupt is pending
	begin
		iir[`UART_II_IP] <= #1 1'b1;
	end
end

endmodule