ax88796_8h-source.html

avr cpu 库源代码 对avr单片机编程很有帮助

00105 <span class="preprocessor"></span><span class="preprocessor">#define  PRX        0x01</span>
00106 <span class="preprocessor"></span><span class="comment">// AX88796 TEST Register Bit Definitions</span>
00107 <span class="preprocessor">#define  AUTOD      0x01 </span>
00108 <span class="preprocessor"></span><span class="preprocessor">#define  RST_B      0x02</span>
00109 <span class="preprocessor"></span><span class="preprocessor">#define  RST_10B    0x04</span>
00110 <span class="preprocessor"></span><span class="preprocessor">#define  RST_TXB    0x08</span>
00111 <span class="preprocessor"></span><span class="comment">// AX88796 GPOC Register Bit Definitions</span>
00112 <span class="preprocessor">#define  GPO0       0x01</span>
00113 <span class="preprocessor"></span><span class="preprocessor">#define  MPSEL      0x10</span>
00114 <span class="preprocessor"></span><span class="preprocessor">#define  MPSET      0x20</span>
00115 <span class="preprocessor"></span><span class="preprocessor">#define  PPDSET     0x40</span>
00116 <span class="preprocessor"></span><span class="comment">// AX88796 MEMR Register Bit Definitions</span>
00117 <span class="preprocessor">#define  MDC        0x01</span>
00118 <span class="preprocessor"></span><span class="preprocessor">#define  MDIR       0x02</span>
00119 <span class="preprocessor"></span><span class="preprocessor">#define  MDI        0x04</span>
00120 <span class="preprocessor"></span><span class="preprocessor">#define  MDO        0x08</span>
00121 <span class="preprocessor"></span><span class="preprocessor">#define  EECS       0x10</span>
00122 <span class="preprocessor"></span><span class="preprocessor">#define  EEI        0x20</span>
00123 <span class="preprocessor"></span><span class="preprocessor">#define  EEO        0x40</span>
00124 <span class="preprocessor"></span><span class="preprocessor">#define  EECLK      0x80</span>
00125 <span class="preprocessor"></span><span class="comment">// AX88796 GPI Register Bit Definitions</span>
00126 <span class="preprocessor">#define  GPI2       0x40</span>
00127 <span class="preprocessor"></span><span class="preprocessor">#define  GPI1       0x20</span>
00128 <span class="preprocessor"></span><span class="preprocessor">#define  GPI0       0x10</span>
00129 <span class="preprocessor"></span><span class="preprocessor">#define  I_SPD      0x04</span>
00130 <span class="preprocessor"></span><span class="preprocessor">#define  I_DPX      0x02</span>
00131 <span class="preprocessor"></span><span class="preprocessor">#define  I_LINK     0x01</span>
00132 <span class="preprocessor"></span><span class="comment">// AX88796 TCR Register Bit Definitions</span>
00133 <span class="preprocessor">#define  FDU        0x80    // full duplex</span>
00134 <span class="preprocessor"></span><span class="preprocessor">#define  PD         0x40    // pad disable</span>
00135 <span class="preprocessor"></span><span class="preprocessor">#define  RLO        0x20    // retry of late collisions</span>
00136 <span class="preprocessor"></span><span class="preprocessor">#define  LB1        0x04    // loopback 1</span>
00137 <span class="preprocessor"></span><span class="preprocessor">#define  LB0        0x02    // loopback 0</span>
00138 <span class="preprocessor"></span><span class="preprocessor">#define  CRC        0x01    // generate CRC</span>
00139 <span class="preprocessor"></span>
00140 <span class="comment">// AX88796 Initial Register Values</span>
00141 <span class="comment">// RCR : INT trigger active high and Accept Broadcast ENET packets</span>
00142 <span class="preprocessor">#define RCR_INIT        (INTT | AB)</span>
00143 <span class="preprocessor"></span><span class="preprocessor">#define DCR_INIT        0x00   // was 0x58 for realtek RTL8019</span>
00144 <span class="preprocessor"></span><span class="comment">// TCR : default transmit operation - CRC is generated</span>
00145 <span class="preprocessor">#define TCR_INIT        0x00</span>
00146 <span class="preprocessor"></span><span class="comment">// IMR : interrupt enabled for receive and overrun events</span>
00147 <span class="preprocessor">#define IMR_INIT        0x11    // PRX and OVW interrupt enabled</span>
00148 <span class="preprocessor"></span><span class="comment">// buffer boundaries</span>
00149 <span class="comment">//  transmit has 6 256-byte pages</span>
00150 <span class="comment">//  receive has 26 256-byte pages</span>
00151 <span class="comment">//  entire available packet buffer space is allocated</span>
00152 <span class="preprocessor">#define TXSTART_INIT    0x40</span>
00153 <span class="preprocessor"></span><span class="preprocessor">#define RXSTART_INIT    0x46</span>
00154 <span class="preprocessor"></span><span class="preprocessor">#define RXSTOP_INIT     0x60</span>
00155 <span class="preprocessor"></span>
00156 <span class="comment">// Ethernet constants</span>
00157 <span class="preprocessor">#define ETHERNET_MIN_PACKET_LENGTH  0x3C</span>
00158 <span class="preprocessor"></span><span class="comment">//#define ETHERNET_HEADER_LENGTH        0x0E</span>
00159 
00160 <span class="comment">// offsets into ax88796 ethernet packet header</span>
00161 <span class="preprocessor">#define  PKTHEADER_STATUS       0x00    // packet status</span>
00162 <span class="preprocessor"></span><span class="preprocessor">#define  PKTHEADER_NEXTPAGE     0x01    // next buffer page</span>
00163 <span class="preprocessor"></span><span class="preprocessor">#define  PKTHEADER_PKTLENL      0x02    // packet length low</span>
00164 <span class="preprocessor"></span><span class="preprocessor">#define  PKTHEADER_PKTLENH      0x03    // packet length high</span>
00165 <span class="preprocessor"></span>
00166 
00167 <span class="comment">// functions</span>
00168 <span class="preprocessor">#include "<a class="code" href="nic_8h.html">nic.h</a>"</span>
00169 
00170 <span class="comment">// setup ports for I/O</span>
00171 <span class="keywordtype">void</span> ax88796SetupPorts(<span class="keywordtype">void</span>);
00172 
00173 <span class="comment">// read ax88796 register</span>
00174 u08 ax88796Read(u08 address);
00175 
00176 <span class="comment">// write ax88796 register</span>
00177 <span class="keywordtype">void</span> ax88796Write(u08 address, u08 data);
00178 
00179 <span class="comment">// initialize the ethernet interface for transmit/receive</span>
00180 <span class="keywordtype">void</span> ax88796Init(<span class="keywordtype">void</span>);
00181 
00182 <span class="comment">// packet transmit functions</span>
00183 <span class="keywordtype">void</span> ax88796BeginPacketSend(<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> packetLength);
00184 <span class="keywordtype">void</span> ax88796SendPacketData(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> * localBuffer, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length);
00185 <span class="keywordtype">void</span> ax88796EndPacketSend(<span class="keywordtype">void</span>);
00186 
00187 <span class="comment">// packet receive functions</span>
00188 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> ax88796BeginPacketRetreive(<span class="keywordtype">void</span>);
00189 <span class="keywordtype">void</span> ax88796RetreivePacketData(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> *localBuffer, <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> length);
00190 <span class="keywordtype">void</span> ax88796EndPacketRetreive(<span class="keywordtype">void</span>);
00191 
00192 <span class="comment">// Processes AX88796 interrupts.</span>
00193 <span class="comment">// Currently, this function looks only for a receive overflow condition.</span>
00194 <span class="comment">// The function need not be called in response to an interrupt,</span>
00195 <span class="comment">// but can be executed just before checking the receive buffer for incoming packets.</span>
00196 <span class="keywordtype">void</span> ax88796ProcessInterrupt(<span class="keywordtype">void</span>);
00197 
00198 <span class="comment">// execute procedure for recovering from a receive overflow</span>
00199 <span class="comment">// this should be done when the receive memory fills up with packets</span>
00200 <span class="keywordtype">void</span> ax88796ReceiveOverflowRecover(<span class="keywordtype">void</span>);
00201 
00202 <span class="comment">// Write MII Registers</span>
00203 <span class="keywordtype">void</span> ax88796WriteMii(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> phyad,<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> regad,<span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> mii_data);
00204 <span class="comment">// Read MII Registers</span>
00205 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> ax88796ReadMii(<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> phyad,<span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> regad);
00206 
00207 <span class="comment">// formatted print of all important AX88796 registers</span>
00208 <span class="keywordtype">void</span> ax88796RegDump(<span class="keywordtype">void</span>);
00209 
00210 <span class="preprocessor">#endif</span>
00211 <span class="preprocessor"></span><span class="comment">//@}</span>
</span></pre></div><hr size="1"><address style="align: right;"><small>Generated on Sun Oct 29 03:41:07 2006 for Procyon AVRlib by&nbsp;
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