📄 dsp56f805.def
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PWMA_PWMVAL2 equ PWMA_BASE+$8 ;PWM Value register 2
PWMA_PWMVAL3 equ PWMA_BASE+$9 ;PWM Value register 3
PWMA_PWMVAL4 equ PWMA_BASE+$A ;PWM Value register 4
PWMA_PWMVAL5 equ PWMA_BASE+$B ;PWM Value register 5
PWMA_PMDEADTM equ PWMA_BASE+$C ;PWM Dead timer register
PWMA_PMDISMAP1 equ PWMA_BASE+$D ;PWM Dissable Mapping register 1
PWMA_PMDISMAP2 equ PWMA_BASE+$E ;PWM Dissable Mapping register 2
PWMA_PMCFG equ PWMA_BASE+$F ;PWM Config register
PWMA_PMCCR equ PWMA_BASE+$10 ;PWM Channel control register
PWMA_PMPORT equ PWMA_BASE+$11 ;PWM Port register
; ------ PWM B ------
PWMB_PMCTL equ PWMB_BASE+$0 ;PWM Control register
PWMB_PMFCTL equ PWMB_BASE+$1 ;PWM Fault control register
PWMB_PMFSA equ PWMB_BASE+$2 ;PWM Fault status acknowledge register
PWMB_PMOUT equ PWMB_BASE+$3 ;PWM Output control register
PWMB_PMCNT equ PWMB_BASE+$4 ;PWM Counter register
PWMB_PWMCM equ PWMB_BASE+$5 ;PWM Counter modulo register
PWMB_PWMVAL0 equ PWMB_BASE+$6 ;PWM Value register 0
PWMB_PWMVAL1 equ PWMB_BASE+$7 ;PWM Value register 1
PWMB_PWMVAL2 equ PWMB_BASE+$8 ;PWM Value register 2
PWMB_PWMVAL3 equ PWMB_BASE+$9 ;PWM Value register 3
PWMB_PWMVAL4 equ PWMB_BASE+$A ;PWM Value register 4
PWMB_PWMVAL5 equ PWMB_BASE+$B ;PWM Value register 5
PWMB_PMDEADTM equ PWMB_BASE+$C ;PWM Dead timer register
PWMB_PMDISMAP1 equ PWMB_BASE+$D ;PWM Dissable Mapping register 1
PWMB_PMDISMAP2 equ PWMB_BASE+$E ;PWM Dissable Mapping register 2
PWMB_PMCFG equ PWMB_BASE+$F ;PWM Config register
PWMB_PMCCR equ PWMB_BASE+$10 ;PWM Channel control register
PWMB_PMPORT equ PWMB_BASE+$11 ;PWM Port register
; ------ DECODER 0 ------
QD0_DECCR equ DEC0_BASE+$0 ;decoder control register
QD0_FIR equ DEC0_BASE+$1 ;filter interval register
QD0_WTR equ DEC0_BASE+$2 ;watchdog timeout register
QD0_POSD equ DEC0_BASE+$3 ;position difference counter register
QD0_POSDH equ DEC0_BASE+$4 ;position difference counter hold register
QD0_REV equ DEC0_BASE+$5 ;revolution counter register
QD0_REVH equ DEC0_BASE+$6 ;revolution hold register
QD0_UPOS equ DEC0_BASE+$7 ;upper position counter register
QD0_LPOS equ DEC0_BASE+$8 ;lower position counter register
QD0_UPOSH equ DEC0_BASE+$9 ;upper position hold register
QD0_LPOSH equ DEC0_BASE+$A ;lower position hold register
QD0_UIR equ DEC0_BASE+$B ;upper initialization register
QD0_LIR equ DEC0_BASE+$C ;lower initialization register
QD0_IMR equ DEC0_BASE+$D ;input monitor register
QD0_TSTREG equ DEC0_BASE+$E ;test register
; ------ DECODER 1 ------
QD1_DECCR equ DEC1_BASE+$0 ;decoder control register
QD1_FIR equ DEC1_BASE+$1 ;filter interval register
QD1_WTR equ DEC1_BASE+$2 ;watchdog timeout register
QD1_POSD equ DEC1_BASE+$3 ;position difference counter register
QD1_POSDH equ DEC1_BASE+$4 ;position difference counter hold register
QD1_REV equ DEC1_BASE+$5 ;revolution counter register
QD1_REVH equ DEC1_BASE+$6 ;revolution hold register
QD1_UPOS equ DEC1_BASE+$7 ;upper position counter register
QD1_LPOS equ DEC1_BASE+$8 ;lower position counter register
QD1_UPOSH equ DEC1_BASE+$9 ;upper position hold register
QD1_LPOSH equ DEC1_BASE+$A ;lower position hold register
QD1_UIR equ DEC1_BASE+$B ;upper initialization register
QD1_LIR equ DEC1_BASE+$C ;lower initialization register
QD1_IMR equ DEC1_BASE+$D ;input monitor register
QD1_TSTREG equ DEC1_BASE+$E ;test register
; ------ ICTN ------
ICTN_GPR0 equ ICTN_BASE+$0 ;Group priority register 0
ICTN_GPR1 equ ICTN_BASE+$1 ;Group priority register 1
ICTN_GPR2 equ ICTN_BASE+$2 ;Group priority register 2
ICTN_GPR3 equ ICTN_BASE+$3 ;Group priority register 3
ICTN_GPR4 equ ICTN_BASE+$4 ;Group priority register 4
ICTN_GPR5 equ ICTN_BASE+$5 ;Group priority register 5
ICTN_GPR6 equ ICTN_BASE+$6 ;Group priority register 6
ICTN_GPR7 equ ICTN_BASE+$7 ;Group priority register 7
ICTN_GPR8 equ ICTN_BASE+$8 ;Group priority register 8
ICTN_GPR9 equ ICTN_BASE+$9 ;Group priority register 9
ICTN_GPR10 equ ICTN_BASE+$A ;Group priority register 10
ICTN_GPR11 equ ICTN_BASE+$B ;Group priority register 11
ICTN_GPR12 equ ICTN_BASE+$C ;Group priority register 12
ICTN_GPR13 equ ICTN_BASE+$D ;Group priority register 13
ICTN_GPR14 equ ICTN_BASE+$E ;Group priority register 14
ICTN_GPR15 equ ICTN_BASE+$F ;Group priority register 15
ICTN_TIRQ0 equ ICTN_BASE+$10 ;Test interrupt request register 0
ICTN_TIRQ1 equ ICTN_BASE+$11 ;Test interrupt request register 1
ICTN_TIRQ2 equ ICTN_BASE+$12 ;Test interrupt request register 2
ICTN_TIRQ3 equ ICTN_BASE+$13 ;Test interrupt request register 3
ICTN_TISR0 equ ICTN_BASE+$18 ;Test interrupt source register 0
ICTN_TISR1 equ ICTN_BASE+$19 ;Test interrupt source register 1
ICTN_TISR2 equ ICTN_BASE+$1A ;Test interrupt source register 2
ICTN_TISR3 equ ICTN_BASE+$1B ;Test interrupt source register 3
ICTN_TCSR equ ICTN_BASE+$1C ;Test control and status register
; ------ ADC A ------
ADCA_ADCR1 equ ADCA_BASE+$0 ;ADC control register 1
ADCA_ADCR2 equ ADCA_BASE+$1 ;ADC control register 2
ADCA_ADZCC equ ADCA_BASE+$2 ;ADC zero crossing control register
ADCA_ADLST1 equ ADCA_BASE+$3 ;ADC channel list register 1
ADCA_ADLST2 equ ADCA_BASE+$4 ;ADC channel list register 2
ADCA_ADSDIS equ ADCA_BASE+$5 ;ADC sample disable register
ADCA_ADSTAT equ ADCA_BASE+$6 ;ADC status register
ADCA_ADLSTAT equ ADCA_BASE+$7 ;ADC limit status register
ADCA_ADZCSTAT equ ADCA_BASE+$8 ;ADC zero crossing status register
ADCA_ADRSLT0 equ ADCA_BASE+$9 ;ADC result register 0
ADCA_ADRSLT1 equ ADCA_BASE+$A ;ADC result register 1
ADCA_ADRSLT2 equ ADCA_BASE+$B ;ADC result register 2
ADCA_ADRSLT3 equ ADCA_BASE+$C ;ADC result register 3
ADCA_ADRSLT4 equ ADCA_BASE+$D ;ADC result register 4
ADCA_ADRSLT5 equ ADCA_BASE+$E ;ADC result register 5
ADCA_ADRSLT6 equ ADCA_BASE+$F ;ADC result register 6
ADCA_ADRSLT7 equ ADCA_BASE+$10 ;ADC result register 7
ADCA_ADLLMT0 equ ADCA_BASE+$11 ;ADC low limit register 0
ADCA_ADLLMT1 equ ADCA_BASE+$12 ;ADC low limit register 1
ADCA_ADLLMT2 equ ADCA_BASE+$13 ;ADC low limit register 2
ADCA_ADLLMT3 equ ADCA_BASE+$14 ;ADC low limit register 3
ADCA_ADLLMT4 equ ADCA_BASE+$15 ;ADC low limit register 4
ADCA_ADLLMT5 equ ADCA_BASE+$16 ;ADC low limit register 5
ADCA_ADLLMT6 equ ADCA_BASE+$17 ;ADC low limit register 6
ADCA_ADLLMT7 equ ADCA_BASE+$18 ;ADC low limit register 7
ADCA_ADHLMT0 equ ADCA_BASE+$19 ;ADC high limit register 0
ADCA_ADHLMT1 equ ADCA_BASE+$1A ;ADC high limit register 1
ADCA_ADHLMT2 equ ADCA_BASE+$1B ;ADC high limit register 2
ADCA_ADHLMT3 equ ADCA_BASE+$1C ;ADC high limit register 3
ADCA_ADHLMT4 equ ADCA_BASE+$1D ;ADC high limit register 4
ADCA_ADHLMT5 equ ADCA_BASE+$1E ;ADC high limit register 5
ADCA_ADHLMT6 equ ADCA_BASE+$1F ;ADC high limit register 6
ADCA_ADHLMT7 equ ADCA_BASE+$20 ;ADC high limit register 7
ADCA_ADOFS0 equ ADCA_BASE+$21 ;ADC offset register 0
ADCA_ADOFS1 equ ADCA_BASE+$22 ;ADC offset register 1
ADCA_ADOFS2 equ ADCA_BASE+$23 ;ADC offset register 2
ADCA_ADOFS3 equ ADCA_BASE+$24 ;ADC offset register 3
ADCA_ADOFS4 equ ADCA_BASE+$25 ;ADC offset register 4
ADCA_ADOFS5 equ ADCA_BASE+$26 ;ADC offset register 5
ADCA_ADOFS6 equ ADCA_BASE+$27 ;ADC offset register 6
ADCA_ADOFS7 equ ADCA_BASE+$28 ;ADC offset register 7
; ------ SCI 0 ------
SCI0_SCIBR equ SCI0_BASE+$0 ;SCI Baud Rate register
SCI0_SCICR equ SCI0_BASE+$1 ;SCI Control register
SCI0_SCISR equ SCI0_BASE+$2 ;SCI Status register
SCI0_SCIDR equ SCI0_BASE+$3 ;SCI Data register
; ------ SCI 1 ------
SCI1_SCIBR equ SCI1_BASE+$0 ;SCI Baud Rate register
SCI1_SCICR equ SCI1_BASE+$1 ;SCI Control register
SCI1_SCISR equ SCI1_BASE+$2 ;SCI Status register
SCI1_SCIDR equ SCI1_BASE+$3 ;SCI Data register
; ------ SPI ------
SPI_SCR equ SPI_BASE+$0 ;SPI status and control register
SPI_DSR equ SPI_BASE+$1 ;SPI data size register
SPI_DRR equ SPI_BASE+$2 ;SPI data receive register
SPI_DTR equ SPI_BASE+$3 ;SPI data transmit register
; ------ COP timer ------
COP_CTL equ COP_BASE+$0 ;COP control register
COP_TO equ COP_BASE+$1 ;COP time out register
COP_SRV equ COP_BASE+$2 ;COP service register
; ------ PFLASH ------
PFIU_CNTL equ PFIU_BASE+$0 ;program flash control register
PFIU_PE equ PFIU_BASE+$1 ;program flash program enable register
PFIU_EE equ PFIU_BASE+$2 ;program flash erase enable register
PFIU_ADDR equ PFIU_BASE+$3 ;program flash address register
PFIU_DATA equ PFIU_BASE+$4 ;program flash data register
PFIU_IE equ PFIU_BASE+$5 ;program flash interrupt enable register
PFIU_IS equ PFIU_BASE+$6 ;program flash interrupt source register
PFIU_IP equ PFIU_BASE+$7 ;program flash interrupt pending register
PFIU_CKDIVISOR equ PFIU_BASE+$8 ;program flash clock divisor register
PFIU_TERASEL equ PFIU_BASE+$9 ;program flash terase limit register
PFIU_TMEL equ PFIU_BASE+$A ;program flash time limit register
PFIU_TNVSL equ PFIU_BASE+$B ;program flash Tnvs limit register
PFIU_TPGSL equ PFIU_BASE+$C ;program flash Tpgs limit register
PFIU_TPROGL equ PFIU_BASE+$D ;program flash Tprog limit register
PFIU_TNVHL equ PFIU_BASE+$E ;program flash TNVH limit register
PFIU_TNVH1L equ PFIU_BASE+$F ;program flash TNVH1 limit register
PFIU_TRCVL equ PFIU_BASE+$10 ;program flash TRCV limit register
; ------ DFLASH ------
DFIU_CNTL equ DFIU_BASE+$0 ;data flash control register
DFIU_PE equ DFIU_BASE+$1 ;data flash enable register
DFIU_EE equ DFIU_BASE+$2 ;data flash erase enable register
DFIU_ADDR equ DFIU_BASE+$3 ;data flash address register
DFIU_DATA equ DFIU_BASE+$4 ;data flash data register
DFIU_IE equ DFIU_BASE+$5 ;data flash interrupt enable register
DFIU_IS equ DFIU_BASE+$6 ;data flash interrupt source register
DFIU_IP equ DFIU_BASE+$7 ;data flash interrupt pending register
DFIU_CKDIVISOR equ DFIU_BASE+$8 ;data flash clock divisor register
DFIU_TERASEL equ DFIU_BASE+$9 ;data flash terase limit register
DFIU_TMEL equ DFIU_BASE+$A ;data flash TME limit register
DFIU_TNVSL equ DFIU_BASE+$B ;data flsh TNVS limit register
DFIU_TPGSL equ DFIU_BASE+$C ;data flash TPGS limit register
DFIU_TPROGL equ DFIU_BASE+$D ;data flsh TPROG limit register
DFIU_TNVHL equ DFIU_BASE+$E ;data flash TNVH limit register
DFIU_TNVHL1 equ DFIU_BASE+$F ;data flash TNVH1 limit register
DFIU_TRCVL equ DFIU_BASE+$10 ;data flash TRCV limit register
; ------ BFLASH ------
BFIU_CNTL equ BFIU_BASE+$0 ;boot flash control register
BFIU_PE equ BFIU_BASE+$1 ;boot flash program enable register
BFIU_EE equ BFIU_BASE+$2 ;boot flash erase enable register
BFIU_ADDR equ BFIU_BASE+$3 ;boot flash address register
BFIU_DATA equ BFIU_BASE+$4 ;boot flash data register
BFIU_IE equ BFIU_BASE+$5 ;boot flash interrupt enable register
BFIU_IS equ BFIU_BASE+$6 ;boot flash interrupt source register
BFIU_IP equ BFIU_BASE+$7 ;boot flash interrupt pending register
BFIU_CKDIVISOR equ BFIU_BASE+$8 ;boot flash clock divisor register
BFIU_TERASEL equ BFIU_BASE+$9 ;boot flash terase limit register
BFIU_TMEL equ BFIU_BASE+$A ;boot flash TME limit register
BFIU_TNVSL equ BFIU_BASE+$B ;boot flash TNVS limit register
BFIU_TPGSL equ BFIU_BASE+$C ;boot flash TPGS limit register
BFIU_TPROGL equ BFIU_BASE+$D ;boot flash TPROG limit register
BFIU_TNVHL equ BFIU_BASE+$E ;boot flash TNVH limit register
BFIU_TNVHL1 equ BFIU_BASE+$F ;boot flash TNVH1 limit register
BFIU_TRCVL equ BFIU_BASE+$10 ;boot flash TRCV limit register
; ------ PLL ------
PLL_CR equ CLKGEN_BASE+$0 ;PLL control register
PLL_DB equ CLKGEN_BASE+$1 ;PLL divide-by register
PLL_SR equ CLKGEN_BASE+$2 ;PLL status register
PLL_TESTR equ CLKGEN_BASE+$3 ;Test register
PLL_CLKOSR equ CLKGEN_BASE+$4 ;CLKO select register
PLL_ISOCTL equ CLKGEN_BASE+$5 ;Internal oscillator ctrl reg
; ------ GPIO ------
GPIOA_PUR equ GPIOA_BASE+$0 ;Pull up enable register
GPIOA_DR equ GPIOA_BASE+$1 ;Data register
GPIOA_DDR equ GPIOA_BASE+$2 ;Data direction register
GPIOA_PER equ GPIOA_BASE+$3 ;Peripheral enable register
GPIOA_IAR equ GPIOA_BASE+$4 ;Interrupt assert register
GPIOA_IENR equ GPIOA_BASE+$5 ;Interrupt enable register
GPIOA_IPOLR equ GPIOA_BASE+$6 ;Interrupt polarity register
GPIOA_IPR equ GPIOA_BASE+$7 ;Interrupt pending register
GPIOA_IESR equ GPIOA_BASE+$8 ;Interrupt edge-sensitive register
GPIOB_PUR equ GPIOB_BASE+$0 ;Pull up enable register
GPIOB_DR equ GPIOB_BASE+$1 ;Data register
GPIOB_DDR equ GPIOB_BASE+$2 ;Data direction register
GPIOB_PER equ GPIOB_BASE+$3 ;Peripheral enable register
GPIOB_IAR equ GPIOB_BASE+$4 ;Interrupt assert register
GPIOB_IENR equ GPIOB_BASE+$5 ;Interrupt enable register
GPIOB_IPOLR equ GPIOB_BASE+$6 ;Interrupt polarity register
GPIOB_IPR equ GPIOB_BASE+$7 ;Interrupt pending register
GPIOB_IESR equ GPIOB_BASE+$8 ;Interrupt edge-sensitive register
GPIOD_PUR equ GPIOD_BASE+$0 ;Pull up enable register
GPIOD_DR equ GPIOD_BASE+$1 ;Data register
GPIOD_DDR equ GPIOD_BASE+$2 ;Data direction register
GPIOD_PER equ GPIOD_BASE+$3 ;Peripheral enable register
GPIOD_IAR equ GPIOD_BASE+$4 ;Interrupt assert register
GPIOD_IENR equ GPIOD_BASE+$5 ;Interrupt enable register
GPIOD_IPOLR equ GPIOD_BASE+$6 ;Interrupt polarity register
GPIOD_IPR equ GPIOD_BASE+$7 ;Interrupt pending register
GPIOD_IESR equ GPIOD_BASE+$8 ;Interrupt edge-sensitive register
GPIOE_PUR equ GPIOE_BASE+$0 ;Pull up enable register
GPIOE_DR equ GPIOE_BASE+$1 ;Data register
GPIOE_DDR equ GPIOE_BASE+$2 ;Data direction register
GPIOE_PER equ GPIOE_BASE+$3 ;Peripheral enable register
GPIOE_IAR equ GPIOE_BASE+$4 ;Interrupt assert register
GPIOE_IENR equ GPIOE_BASE+$5 ;Interrupt enable register
GPIOE_IPOLR equ GPIOE_BASE+$6 ;Interrupt polarity register
GPIOE_IPR equ GPIOE_BASE+$7 ;Interrupt pending register
GPIOE_IESR equ GPIOE_BASE+$8 ;Interrupt edge-sensitive register
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