📄 dsp56f805.def
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; DSP56F805 register definitions
OPGDBR equ x:$FFFF ;OnCE PGDB bus transfer register
IPR equ x:$FFFB ;interrupt priority register
BCR equ x:$FFF9 ;bus control register
SYS_BASE equ $0C00 ;system contrl registers
TMRA_BASE equ $0D00 ;quad timer A registers
TMRB_BASE equ $0D20 ;quad timer B registers
TMRC_BASE equ $0D40 ;quad timer C registers
TMRD_BASE equ $0D60 ;quad timer D registers
CAN_BASE equ $0D80 ;CAN
COP_BASE equ $0F30 ;COP timer
GPIOA_BASE equ $0FB0 ;GPIO A
GPIOB_BASE equ $0FC0 ;GPIO B
GPIOD_BASE equ $0FE0 ;GPIO D
GPIOE_BASE equ $0FF0 ;GPIO E
CLKGEN_BASE equ $0FA0 ;PLL
SPI_BASE equ $0F20 ;SPI
PWMA_BASE equ $0E00 ;PWM A
PWMB_BASE equ $0E20 ;PWM B
ICTN_BASE equ $0E60 ;Interrupt controller
ADCA_BASE equ $0E80 ;ADC A
SCI0_BASE equ $0F00 ;SCI 0
SCI1_BASE equ $0F10 ;SCI 1
DEC0_BASE equ $0E40 ;Quadrature decoder 0 base address
DEC1_BASE equ $0E50 ;Quadrature decoder 1 base address
PFIU_BASE equ $0F40 ;Program flash interface unit base address
DFIU_BASE equ $0F60 ;Data flash interface unit base address
BFIU_BASE equ $0F80 ;Boot block flash interface unit base addr
; ------ System Control Registers -----
SYS_CTRL equ SYS_BASE+$0 ;system control register
SYS_STS equ SYS_BASE+$1 ;system status register
; ------ Timers ------
TMRA0_CMP1 equ TMRA_BASE+$0 ;Timer A0 compare register 1
TMRA0_CMP2 equ TMRA_BASE+$1 ;Timer A0 compare register 2
TMRA0_CAP equ TMRA_BASE+$2 ;Timer A0 capture register
TMRA0_LOAD equ TMRA_BASE+$3 ;Timer A0 load register
TMRA0_HOLD equ TMRA_BASE+$4 ;Timer A0 hold register
TMRA0_CNTR equ TMRA_BASE+$5 ;Timer A0 counter register
TMRA0_CTRL equ TMRA_BASE+$6 ;Timer A0 control register
TMRA0_SCR equ TMRA_BASE+$7 ;Timer A0 status and control register
TMRA1_CMP1 equ TMRA_BASE+$8 ;Timer A1 compare register 1
TMRA1_CMP2 equ TMRA_BASE+$9 ;Timer A1 compare register 2
TMRA1_CAP equ TMRA_BASE+$A ;Timer A1 capture register
TMRA1_LOAD equ TMRA_BASE+$B ;Timer A1 load register
TMRA1_HOLD equ TMRA_BASE+$C ;Timer A1 hold register
TMRA1_CNTR equ TMRA_BASE+$D ;Timer A1 counter register
TMRA1_CTRL equ TMRA_BASE+$E ;Timer A1 control register
TMRA1_SCR equ TMRA_BASE+$F ;Timer A1 status and control register
TMRA2_CMP1 equ TMRA_BASE+$10 ;Timer A2 compare register 1
TMRA2_CMP2 equ TMRA_BASE+$11 ;Timer A2 compare register 2
TMRA2_CAP equ TMRA_BASE+$12 ;Timer A2 capture register
TMRA2_LOAD equ TMRA_BASE+$13 ;Timer A2 load register
TMRA2_HOLD equ TMRA_BASE+$14 ;Timer A2 hold register
TMRA2_CNTR equ TMRA_BASE+$15 ;Timer A2 counter register
TMRA2_CTRL equ TMRA_BASE+$16 ;Timer A2 control register
TMRA2_SCR equ TMRA_BASE+$17 ;Timer A2 status and control register
TMRA3_CMP1 equ TMRA_BASE+$18 ;Timer A3 compare register 1
TMRA3_CMP2 equ TMRA_BASE+$19 ;Timer A3 compare register 2
TMRA3_CAP equ TMRA_BASE+$1A ;Timer A3 capture register
TMRA3_LOAD equ TMRA_BASE+$1B ;Timer A3 load register
TMRA3_HOLD equ TMRA_BASE+$1C ;Timer A3 hold register
TMRA3_CNTR equ TMRA_BASE+$1D ;Timer A3 counter register
TMRA3_CTRL equ TMRA_BASE+$1E ;Timer A3 control register
TMRA3_SCR equ TMRA_BASE+$1F ;Timer A3 status and control register
TMRB0_CMP1 equ TMRB_BASE+$0 ;Timer B0 compare register 1
TMRB0_CMP2 equ TMRB_BASE+$1 ;Timer B0 compare register 2
TMRB0_CAP equ TMRB_BASE+$2 ;Timer B0 capture register
TMRB0_LOAD equ TMRB_BASE+$3 ;Timer B0 load register
TMRB0_HOLD equ TMRB_BASE+$4 ;Timer B0 hold register
TMRB0_CNTR equ TMRB_BASE+$5 ;Timer B0 counter register
TMRB0_CTRL equ TMRB_BASE+$6 ;Timer B0 control register
TMRB0_SCR equ TMRB_BASE+$7 ;Timer B0 status and control register
TMRB1_CMP1 equ TMRB_BASE+$8 ;Timer B1 compare register 1
TMRB1_CMP2 equ TMRB_BASE+$9 ;Timer B1 compare register 2
TMRB1_CAP equ TMRB_BASE+$A ;Timer B1 capture register
TMRB1_LOAD equ TMRB_BASE+$B ;Timer B1 load register
TMRB1_HOLD equ TMRB_BASE+$C ;Timer B1 hold register
TMRB1_CNTR equ TMRB_BASE+$D ;Timer B1 counter register
TMRB1_CTRL equ TMRB_BASE+$E ;Timer B1 control register
TMRB1_SCR equ TMRB_BASE+$F ;Timer B1 status and control register
TMRB2_CMP1 equ TMRB_BASE+$10 ;Timer B2 compare register 1
TMRB2_CMP2 equ TMRB_BASE+$11 ;Timer B2 compare register 2
TMRB2_CAP equ TMRB_BASE+$12 ;Timer B2 capture register
TMRB2_LOAD equ TMRB_BASE+$13 ;Timer B2 load register
TMRB2_HOLD equ TMRB_BASE+$14 ;Timer B2 hold register
TMRB2_CNTR equ TMRB_BASE+$15 ;Timer B2 counter register
TMRB2_CTRL equ TMRB_BASE+$16 ;Timer B2 control register
TMRB2_SCR equ TMRB_BASE+$17 ;Timer B2 status and control register
TMRB3_CMP1 equ TMRB_BASE+$18 ;Timer B3 compare register 1
TMRB3_CMP2 equ TMRB_BASE+$19 ;Timer B3 compare register 2
TMRB3_CAP equ TMRB_BASE+$1A ;Timer B3 capture register
TMRB3_LOAD equ TMRB_BASE+$1B ;Timer B3 load register
TMRB3_HOLD equ TMRB_BASE+$1C ;Timer B3 hold register
TMRB3_CNTR equ TMRB_BASE+$1D ;Timer B3 counter register
TMRB3_CTRL equ TMRB_BASE+$1E ;Timer B3 control register
TMRB3_SCR equ TMRB_BASE+$1F ;Timer B3 status and control register
TMRC0_CMP1 equ TMRC_BASE+$0 ;Timer C0 compare register 1
TMRC0_CMP2 equ TMRC_BASE+$1 ;Timer C0 compare register 2
TMRC0_CAP equ TMRC_BASE+$2 ;Timer C0 capture register
TMRC0_LOAD equ TMRC_BASE+$3 ;Timer C0 load register
TMRC0_HOLD equ TMRC_BASE+$4 ;Timer C0 hold register
TMRC0_CNTR equ TMRC_BASE+$5 ;Timer C0 counter register
TMRC0_CTRL equ TMRC_BASE+$6 ;Timer C0 control register
TMRC0_SCR equ TMRC_BASE+$7 ;Timer C0 status and control register
TMRC1_CMP1 equ TMRC_BASE+$8 ;Timer C1 compare register 1
TMRC1_CMP2 equ TMRC_BASE+$9 ;Timer C1 compare register 2
TMRC1_CAP equ TMRC_BASE+$A ;Timer C1 capture register
TMRC1_LOAD equ TMRC_BASE+$B ;Timer C1 load register
TMRC1_HOLD equ TMRC_BASE+$C ;Timer C1 hold register
TMRC1_CNTR equ TMRC_BASE+$D ;Timer C1 counter register
TMRC1_CTRL equ TMRC_BASE+$E ;Timer C1 control register
TMRC1_SCR equ TMRC_BASE+$F ;Timer C1 status and control register
TMRC2_CMP1 equ TMRC_BASE+$10 ;Timer C2 compare register 1
TMRC2_CMP2 equ TMRC_BASE+$11 ;Timer C2 compare register 2
TMRC2_CAP equ TMRC_BASE+$12 ;Timer C2 capture register
TMRC2_LOAD equ TMRC_BASE+$13 ;Timer C2 load register
TMRC2_HOLD equ TMRC_BASE+$14 ;Timer C2 hold register
TMRC2_CNTR equ TMRC_BASE+$15 ;Timer C2 counter register
TMRC2_CTRL equ TMRC_BASE+$16 ;Timer C2 control register
TMRC2_SCR equ TMRC_BASE+$17 ;Timer C2 status and control register
TMRC3_CMP1 equ TMRC_BASE+$18 ;Timer C3 compare register 1
TMRC3_CMP2 equ TMRC_BASE+$19 ;Timer C3 compare register 2
TMRC3_CAP equ TMRC_BASE+$1A ;Timer C3 capture register
TMRC3_LOAD equ TMRC_BASE+$1B ;Timer C3 load register
TMRC3_HOLD equ TMRC_BASE+$1C ;Timer C3 hold register
TMRC3_CNTR equ TMRC_BASE+$1D ;Timer C3 counter register
TMRC3_CTRL equ TMRC_BASE+$1E ;Timer C3 control register
TMRC3_SCR equ TMRC_BASE+$1F ;Timer C3 status and control register
TMRD0_CMP1 equ TMRD_BASE+$0 ;Timer D0 compare register 1
TMRD0_CMP2 equ TMRD_BASE+$1 ;Timer D0 compare register 2
TMRD0_CAP equ TMRD_BASE+$2 ;Timer D0 capture register
TMRD0_LOAD equ TMRD_BASE+$3 ;Timer D0 load register
TMRD0_HOLD equ TMRD_BASE+$4 ;Timer D0 hold register
TMRD0_CNTR equ TMRD_BASE+$5 ;Timer D0 counter register
TMRD0_CTRL equ TMRD_BASE+$6 ;Timer D0 control register
TMRD0_SCR equ TMRD_BASE+$7 ;Timer D0 status and control register
TMRD1_CMP1 equ TMRD_BASE+$8 ;Timer D1 compare register 1
TMRD1_CMP2 equ TMRD_BASE+$9 ;Timer D1 compare register 2
TMRD1_CAP equ TMRD_BASE+$A ;Timer D1 capture register
TMRD1_LOAD equ TMRD_BASE+$B ;Timer D1 load register
TMRD1_HOLD equ TMRD_BASE+$C ;Timer D1 hold register
TMRD1_CNTR equ TMRD_BASE+$D ;Timer D1 counter register
TMRD1_CTRL equ TMRD_BASE+$E ;Timer D1 control register
TMRD1_SCR equ TMRD_BASE+$F ;Timer D1 status and control register
TMRD2_CMP1 equ TMRD_BASE+$10 ;Timer D2 compare register 1
TMRD2_CMP2 equ TMRD_BASE+$11 ;Timer D2 compare register 2
TMRD2_CAP equ TMRD_BASE+$12 ;Timer D2 capture register
TMRD2_LOAD equ TMRD_BASE+$13 ;Timer D2 load register
TMRD2_HOLD equ TMRD_BASE+$14 ;Timer D2 hold register
TMRD2_CNTR equ TMRD_BASE+$15 ;Timer D2 counter register
TMRD2_CTRL equ TMRD_BASE+$16 ;Timer D2 control register
TMRD2_SCR equ TMRD_BASE+$17 ;Timer D2 status and control register
TMRD3_CMP1 equ TMRD_BASE+$18 ;Timer D3 compare register 1
TMRD3_CMP2 equ TMRD_BASE+$19 ;Timer D3 compare register 2
TMRD3_CAP equ TMRD_BASE+$1A ;Timer D3 capture register
TMRD3_LOAD equ TMRD_BASE+$1B ;Timer D3 load register
TMRD3_HOLD equ TMRD_BASE+$1C ;Timer D3 hold register
TMRD3_CNTR equ TMRD_BASE+$1D ;Timer D3 counter register
TMRD3_CTRL equ TMRD_BASE+$1E ;Timer D3 control register
TMRD3_SCR equ TMRD_BASE+$1F ;Timer D3 status and control register
; ------ CAN ------
CAN_CTL0 equ CAN_BASE+$0 ;control register 0
CAN_CTL1 equ CAN_BASE+$1 ;control register 1
CAN_BTR0 equ CAN_BASE+$2 ;bus timing register 0
CAN_BTR1 equ CAN_BASE+$3 ;bus timing register 1
CAN_RFLG equ CAN_BASE+$4 ;receiver flag register
CAN_RIER equ CAN_BASE+$5 ;receiver interrupt enable register
CAN_TFLG equ CAN_BASE+$6 ;transmitter flag register
CAN_TCR equ CAN_BASE+$7 ;transmitter control register
CAN_IDAC equ CAN_BASE+$8 ;identifier acceptance control register
CAN_RXERR equ CAN_BASE+$E ;receiver error counter register
CAN_TXERR equ CAN_BASE+$F ;transmit error counter register
CAN_IDAR0 equ CAN_BASE+$10 ;identifier acceptance register 0
CAN_IDAR1 equ CAN_BASE+$11 ;identifier acceptance register 1
CAN_IDAR2 equ CAN_BASE+$12 ;identifier acceptance register 2
CAN_IDAR3 equ CAN_BASE+$13 ;identifier acceptance register 3
CAN_IDAR4 equ CAN_BASE+$18 ;identifier acceptance register 4
CAN_IDAR5 equ CAN_BASE+$19 ;identifier acceptance register 5
CAN_IDAR6 equ CAN_BASE+$1A ;identifier acceptance register 6
CAN_IDAR7 equ CAN_BASE+$1B ;identifier acceptance register 7
CAN_IDMR0 equ CAN_BASE+$14 ;identifier mask register 0
CAN_IDMR1 equ CAN_BASE+$15 ;identifier mask register 1
CAN_IDMR2 equ CAN_BASE+$16 ;identifier mask register 2
CAN_IDMR3 equ CAN_BASE+$17 ;identifier mask register 3
CAN_IDMR4 equ CAN_BASE+$1C ;identifier mask register 4
CAN_IDMR5 equ CAN_BASE+$1D ;identifier mask register 5
CAN_IDMR6 equ CAN_BASE+$1E ;identifier mask register 6
CAN_IDMR7 equ CAN_BASE+$1F ;identifier mask register 7
CAN_RB_IDR0 equ CAN_BASE+$40 ;receive buffer identifier register 0
CAN_RB_IDR1 equ CAN_BASE+$41 ;receive buffer identifier register 1
CAN_RB_IDR2 equ CAN_BASE+$42 ;receive buffer identifier register 2
CAN_RB_IDR3 equ CAN_BASE+$43 ;receive buffer identifier register 3
CAN_RB_SDR0 equ CAN_BASE+$44 ;receive buffer data segment register 0
CAN_RB_SDR1 equ CAN_BASE+$45 ;receive buffer data segment register 1
CAN_RB_SDR2 equ CAN_BASE+$46 ;receive buffer data segment register 2
CAN_RB_SDR3 equ CAN_BASE+$47 ;receive buffer data segment register 3
CAN_RB_SDR4 equ CAN_BASE+$48 ;receive buffer data segment register 4
CAN_RB_SDR5 equ CAN_BASE+$49 ;receive buffer data segment register 5
CAN_RB_SDR6 equ CAN_BASE+$4A ;receive buffer data segment register 6
CAN_RB_SDR7 equ CAN_BASE+$4B ;receive buffer data segment register 7
CAN_RB_DLR equ CAN_BASE+$4C ;receive buffer data length register
CAN_RB_TBPR equ CAN_BASE+$4D ;receive buffer transmit buffer priority register
CAN_TB0_IDR0 equ CAN_BASE+$50 ;transmit buffer 0 identifier register 0
CAN_TB0_IDR1 equ CAN_BASE+$51 ;transmit buffer 0 identifier register 1
CAN_TB0_IDR2 equ CAN_BASE+$52 ;transmit buffer 0 identifier register 2
CAN_TB0_IDR3 equ CAN_BASE+$53 ;transmit buffer 0 identifier register 3
CAN_TB0_DSR0 equ CAN_BASE+$54 ;transmit buffer 0 data segment register 0
CAN_TB0_DSR1 equ CAN_BASE+$55 ;transmit buffer 0 data segment register 1
CAN_TB0_DSR2 equ CAN_BASE+$56 ;transmit buffer 0 data segment register 2
CAN_TB0_DSR3 equ CAN_BASE+$57 ;transmit buffer 0 data segment register 3
CAN_TB0_DSR4 equ CAN_BASE+$58 ;transmit buffer 0 data segment register 4
CAN_TB0_DSR5 equ CAN_BASE+$59 ;transmit buffer 0 data segment register 5
CAN_TB0_DSR6 equ CAN_BASE+$5A ;transmit buffer 0 data segment register 6
CAN_TB0_DSR7 equ CAN_BASE+$5B ;transmit buffer 0 data segment register 7
CAN_TB0_DLR equ CAN_BASE+$5C ;transmit buffer 0 data length register
CAN_TB0_TBPR equ CAN_BASE+$5D ;transmit buffer 0 transmit buffer priority register
CAN_TB1_IDR0 equ CAN_BASE+$60 ;transmit buffer 1 identifier register 0
CAN_TB1_IDR1 equ CAN_BASE+$61 ;transmit buffer 1 identifier register 1
CAN_TB1_IDR2 equ CAN_BASE+$62 ;transmit buffer 1 identifier register 2
CAN_TB1_IDR3 equ CAN_BASE+$63 ;transmit buffer 1 identifier register 3
CAN_TB1_DSR0 equ CAN_BASE+$64 ;transmit buffer 1 data segment register 0
CAN_TB1_DSR1 equ CAN_BASE+$65 ;transmit buffer 1 data segment register 1
CAN_TB1_DSR2 equ CAN_BASE+$66 ;transmit buffer 1 data segment register 2
CAN_TB1_DSR3 equ CAN_BASE+$67 ;transmit buffer 1 data segment register 3
CAN_TB1_DSR4 equ CAN_BASE+$68 ;transmit buffer 1 data segment register 4
CAN_TB1_DSR5 equ CAN_BASE+$69 ;transmit buffer 1 data segment register 5
CAN_TB1_DSR6 equ CAN_BASE+$6A ;transmit buffer 1 data segment register 6
CAN_TB1_DSR7 equ CAN_BASE+$6B ;transmit buffer 1 data segment register 7
CAN_TB1_DLR equ CAN_BASE+$6C ;transmit buffer 1 data length register
CAN_TB1_TBPR equ CAN_BASE+$6D ;transmit buffer 1 transmit buffer priority register
CAN_TB2_IDR0 equ CAN_BASE+$70 ;transmit buffer 2 identifier register 0
CAN_TB2_IDR1 equ CAN_BASE+$71 ;transmit buffer 2 identifier register 1
CAN_TB2_IDR2 equ CAN_BASE+$72 ;transmit buffer 2 identifier register 2
CAN_TB2_IDR3 equ CAN_BASE+$73 ;transmit buffer 2 identifier register 3
CAN_TB2_DSR0 equ CAN_BASE+$74 ;transmit buffer 2 data segment register 0
CAN_TB2_DSR1 equ CAN_BASE+$75 ;transmit buffer 2 data segment register 1
CAN_TB2_DSR2 equ CAN_BASE+$76 ;transmit buffer 2 data segment register 2
CAN_TB2_DSR3 equ CAN_BASE+$77 ;transmit buffer 2 data segment register 3
CAN_TB2_DSR4 equ CAN_BASE+$78 ;transmit buffer 2 data segment register 4
CAN_TB2_DSR5 equ CAN_BASE+$79 ;transmit buffer 2 data segment register 5
CAN_TB2_DSR6 equ CAN_BASE+$7A ;transmit buffer 2 data segment register 6
CAN_TB2_DSR7 equ CAN_BASE+$7B ;transmit buffer 2 data segment register 7
CAN_TB2_DLR equ CAN_BASE+$7C ;transmit buffer 2 data length register
CAN_TB2_TBPR equ CAN_BASE+$7D ;transmit buffer 2 transmit buffer priority register
; ------ PWM A ------
PWMA_PMCTL equ PWMA_BASE+$0 ;PWM Control register
PWMA_PMFCTL equ PWMA_BASE+$1 ;PWM Fault control register
PWMA_PMFSA equ PWMA_BASE+$2 ;PWM Fault status acknowledge register
PWMA_PMOUT equ PWMA_BASE+$3 ;PWM Output control register
PWMA_PMCNT equ PWMA_BASE+$4 ;PWM Counter register
PWMA_PWMCM equ PWMA_BASE+$5 ;PWM Counter modulo register
PWMA_PWMVAL0 equ PWMA_BASE+$6 ;PWM Value register 0
PWMA_PWMVAL1 equ PWMA_BASE+$7 ;PWM Value register 1
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