setup.asm

DSP56F807的CAN通讯程序,可用于多子板互连、也可作为开发的原型程序

	include "DSP56f805.def"
	include "C_compiler.def"

DSP56F803	EQU	0
	
	ORG	P:

	SECTION	Interrupt_Vector_Table 
	
	GLOBAL	IV_Table
	LOCAL	nop_isr
	
IV_Table:	
	IF DSP56F803
	jsr	Start		;irq 0		Hardware reset
	jsr	Start		;irq 1		COP timer
	ENDIF
	jsr	nop_isr		;irq 2		Reserved
	jsr	nop_isr		;irq 3		Illegal instruction
	jsr	nop_isr		;irq 4		Swi
	jsr	nop_isr		;irq 5		Stack overflow
	jsr	nop_isr		;irq 6		Once
	jsr	nop_isr		;irq 7		Reserved
	jsr	nop_isr		;irq 8		Irq A
	jsr	nop_isr		;irq 9		Irq B
	jsr	nop_isr		;irq 10		Reserved
	jsr	nop_isr		;irq 11		Boot Flash
	jsr	nop_isr		;irq 12		Program Flash
	jsr	nop_isr		;irq 13		Data Flash
	jsr	nop_isr		;irq 14		MSCAN Tx Ready
	jsr	Fcan_rx_isr			;irq 15		MSCAN Rx Full
	jsr	nop_isr		;irq 16		MSCAN Error
	jsr	nop_isr		;irq 17		MSCAN Wakeup
	jsr	nop_isr		;irq 18		Reserved
	jsr	nop_isr		;irq 19		GPIO E
	jsr	nop_isr		;irq 20		GPIO D
	jsr	nop_isr		;irq 21		Reserved
	jsr	nop_isr		;irq 22		GPIO B
	jsr	nop_isr		;irq 23		GPIO A
	jsr	nop_isr		;irq 24		SPI Transmitter Empty
	jsr	nop_isr		;irq 25		SPI Rx Full and/or error
	jsr	nop_isr		;irq 26		Quadrature decoder #1 home switch or watchdog
	jsr	nop_isr		;irq 27		Quadrature decoder #1 index pulse
	jsr	nop_isr		;irq 28		Quadrature decoder #0 home switch or watchdog
	jsr	nop_isr		;irq 29		Quadrature decoder #0 index pulse
	jsr	nop_isr		;irq 30		Timer D0
	jsr	nop_isr		;irq 31		Timer D1
	jsr	nop_isr		;irq 32		Timer D2
	jsr	nop_isr		;irq 33		Timer D3
	jsr	nop_isr		;irq 34		Timer C0
	jsr	nop_isr		;irq 35		Timer C1
	jsr	nop_isr		;irq 36		Timer C2
	jsr	nop_isr		;irq 37		Timer C3
	jsr	nop_isr		;irq 38		Timer B0
	jsr	nop_isr		;irq 39		Timer B1
	jsr	nop_isr		;irq 40		Timer B2
	jsr	nop_isr		;irq 41		Timer B3
	jsr	nop_isr		;irq 42		Timer A0
	jsr	nop_isr		;irq 43		Timer A1
	jsr	nop_isr		;irq 44		Timer A2
	jsr	nop_isr		;irq 45		Timer A3
	jsr	nop_isr		;irq 46		SCI #1 Tx Idle
	jsr	nop_isr		;irq 47		SCI #1 Tx Empty
	jsr	nop_isr		;irq 48		SCI #1 Rx Error
	jsr	nop_isr		;irq 49		SCI #1 Rx Full
	jsr	Fsci_tx_idle_isr	;irq 50		SCI #0 Tx Idle
	jsr	Fsci_tx_empty_isr	;irq 51		SCI #0 Tx Empty
	jsr	nop_isr		;irq 52		SCI #0 Rx Error
	jsr	Fsci_rx_isr			;irq 53		SCI #0 Rx Full
	jsr	nop_isr		;irq 54		ADC B Conversion Complete		;ADC B not present on 805
	jsr	nop_isr		;irq 55		ADC A Conversion Complete
	jsr	nop_isr		;irq 56		ADC B Zero crossing/limit error	;ADC B not present on 805
	jsr	nop_isr		;irq 57		ADC A Zero crossing/limit error
	jsr	nop_isr		;irq 58		PWM B Reload
	jsr	nop_isr		;irq 59		PWM A Reload
	jsr	nop_isr		;irq 60		PWM B Fault
	jsr	nop_isr		;irq 61		PWM A Fault
	jsr	nop_isr		;irq 62		PLL Loss of Lock
	jsr	nop_isr		;irq 63		Undervoltage detector

nop_isr:
	nop
	debug	
	rti

	ENDSEC

	SECTION Setup
	
	GLOBAL	Start
	LOCAL	pll_lock
	LOCAL	init_vars
	
Start:
	bfclr	#$0002,x:COP_CTL	;disable COP
	bfclr	#$00ff,x:<<BCR		;set 0 wait states
	move	#F_StackAddr,r0		;init stack (definition in linker cmd file)
	nop
	move	r0,x:<mr15			;for C compiler compatibility
	move	r0,sp
								;PLL setup
	move	#$0081,x:PLL_CR		;PLL lock detector ON, core still on 8 MHz
	move	#$F013,x:PLL_DB		;80 MHz DSP core, 160 MHz VCO, 40 MHz bus
pll_lock:
	brclr	#$0040,x:PLL_SR,pll_lock		;test lock (LCK1)
								;PLL locked
	move	#$0082,x:PLL_CR		;PLL lock detector ON, core on PLL clock
	move    x:PLL_SR,x0			; clear pending CLKGEN interrupts
	move 	x0,x:PLL_SR

	move	#F_Xdata_start_in_ROM,r0	;init global variables
	move	#F_Xdata_start_in_RAM,r1
	move	#F_Xdata_size,x0
	tstw	x0
	beq		init_vars
	
	do		x0,init_vars		;transfer init values from Flash to Ram
	move	x:(r0)+,x0
	move	x0,x:(r1)+
init_vars:
	
	jsr		Fmain			;jump to user program after init

	ENDSEC