📄 main.asm
字号:
ADD .D1 1,A10,A10 ; |59|
|| MVK .S1 6400,A3 ; |59|
CMPLT .L1 A10,A3,A0 ; |59|
[ A0] BNOP .S1 L2,5 ; |59|
; BRANCH OCCURS ; |59|
;** --------------------------------------------------------------------------*
BNOP .S1 L4,5 ; |59|
; BRANCH OCCURS ; |59|
;** --------------------------------------------------------------------------*
L3:
.line 35
CALL .S2 _printf ; |56|
|| MVKL .S1 SL6+0,A4 ; |56|
MVKH .S1 SL6+0,A4 ; |56|
STW .D2T1 A4,*+SP(4) ; |56|
STW .D2T1 A10,*+SP(8) ; |56|
STW .D2T2 B4,*+SP(12) ; |56|
ADDKPC .S2 RL11,B3,0 ; |56|
|| STW .D2T1 A3,*+SP(16) ; |56|
RL11: ; CALL OCCURS ; |56|
.line 34
MVK .D2 0x1,B4 ; |55|
NOP 1
MV .D1X B4,A11 ; |55|
;** --------------------------------------------------------------------------*
L4:
.line 40
MV .D1 A11,A0
[ A0] BNOP .S1 L5,5 ; |61|
; BRANCH OCCURS ; |61|
;** --------------------------------------------------------------------------*
.line 41
CALL .S1 _printf ; |62|
ADDKPC .S2 RL12,B3,1 ; |62|
MVKL .S1 SL7+0,A3 ; |62|
MVKH .S1 SL7+0,A3 ; |62|
STW .D2T1 A3,*+SP(4) ; |62|
RL12: ; CALL OCCURS ; |62|
;** --------------------------------------------------------------------------*
L5:
.line 43
LDW .D2T2 *+SP(40),B3 ; |64|
MV .D1X SP,A31 ; |64|
LDDW .D1T1 *+A31(24),A11:A10 ; |64|
LDW .D2T2 *+SP(44),B10 ; |64|
LDDW .D1T1 *+A31(32),A13:A12 ; |64|
RET .S2 B3 ; |64|
LDW .D2T2 *++SP(48),B11 ; |64|
NOP 4
; BRANCH OCCURS ; |64|
.endfunc 64,00c083c00h,48
.sect ".text"
.global _osd_c
.sym _osd_c,_osd_c, 32, 2, 0
.func 66
;******************************************************************************
;* FUNCTION NAME: _osd_c *
;* *
;* Regs Modified : A0,A1,A3,A4,B0,B1,B4,B5 *
;* Regs Used : A0,A1,A3,A4,A6,B0,B1,B3,B4,B5 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o2) may disable key optimizations! *
;* *
;******************************************************************************
_osd_c:
;** --------------------------------------------------------------------------*
.line 2
.sym _pIn0,4, 28, 17, 32
.sym _pMask,20, 28, 17, 32
.sym _longth,6, 4, 17, 32
.sym _pMask,3, 28, 4, 32
.sym _pIn0,4, 28, 4, 32
.sym _pIn0,3, 28, 4, 32
.sym _pMask,3, 28, 4, 32
.sym _longth,16, 4, 4, 32
MV .D2X A6,B0 ; |67|
|| MV .D1X B4,A3 ; |67|
.line 9
CMPGT .L2 B0,0,B1 ; |74|
[!B1] BNOP .S1 L10,5 ; |74|
; BRANCH OCCURS ; |74|
;** --------------------------------------------------------------------------*
.line 13
CMPGT .L2 B0,6,B1
[ B1] B .S1 L7
[!B1] LDBU .D1T1 *A3++,A0
NOP 4
; BRANCH OCCURS
;** --------------------------------------------------------------------------*
;** BEGIN LOOP L6
;** --------------------------------------------------------------------------*
L6:
.line 15
[ A0] STB .D1T1 A0,*A4 ; |80|
.line 18
ADD .D1 1,A4,A4 ; |83|
.line 19
SUB .D2 B0,1,B0 ; |84|
[ B0] B .S1 L6 ; |84|
[ B0] LDBU .D1T1 *A3++,A0
NOP 4
; BRANCH OCCURS ; |84|
;** --------------------------------------------------------------------------*
BNOP .S1 L10,5
; BRANCH OCCURS
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 74
;* Loop opening brace source line : 75
;* Loop closing brace source line : 84
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 0
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 1
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 1* 0
;* .D units 1* 1*
;* .M units 0 0
;* .X cross paths 0 1*
;* .T address paths 1* 1*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 2 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1* 0
;* Bound(.L .S .D .LS .LSD) 1* 1*
;*
;* Searching for software pipeline schedule at ...
;* ii = 1 Schedule found with 7 iterations in parallel
;* Done
;*
;* Epilog not removed
;* Collapsed epilog stages : 0
;*
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* For further improvement on this loop, try option -mh6
;*
;* Minimum safe trip count : 7
;*----------------------------------------------------------------------------*
L7: ; PIPED LOOP PROLOG
SUB .S1X B0,7,A1
|| LDBU .D1T1 *A3++,A4 ; (P) <0,0>
LDBU .D1T1 *A3++,A4 ; (P) <1,0>
|| [ A1] BDEC .S1 L8,A1 ; |84| (P) <0,1>
[ A1] BDEC .S1 L8,A1 ; |84| (P) <1,1>
|| LDBU .D1T1 *A3++,A4 ; (P) <2,0>
LDBU .D1T1 *A3++,A4 ; (P) <3,0>
|| [ A1] BDEC .S1 L8,A1 ; |84| (P) <2,1>
MV .D2X A4,B4
|| [ A1] BDEC .S1 L8,A1 ; |84| (P) <3,1>
|| LDBU .D1T1 *A3++,A4 ; (P) <4,0>
MV .L1 A4,A0 ; (P) <0,5> Split a long life
|| ADD .D2 1,B4,B4 ; (P) <0,5>
|| MV .S2X A4,B5 ; (P) <0,5> Define a twin register
|| LDBU .D1T1 *A3++,A4 ; (P) <5,0>
|| [ A1] BDEC .S1 L8,A1 ; |84| (P) <4,1>
;** --------------------------------------------------------------------------*
L8: ; PIPED LOOP KERNEL
[ A0] STB .D2T2 B5,*-B4(1) ; |80| <0,6>
|| MV .L1 A4,A0 ; <1,5> Split a long life
|| ADD .S2 1,B4,B4 ; <1,5>
|| MV .L2X A4,B5 ; <1,5> Define a twin register
|| [ A1] BDEC .S1 L8,A1 ; |84| <5,1>
|| LDBU .D1T1 *A3++,A4 ; <6,0>
;** --------------------------------------------------------------------------*
L9: ; PIPED LOOP EPILOG
MV .D1 A4,A0 ; (E) <2,5> Split a long life
|| ADD .S2 1,B4,B4 ; (E) <2,5>
|| MV .L2X A4,B5 ; (E) <2,5> Define a twin register
|| [ A0] STB .D2T2 B5,*-B4(1) ; |80| (E) <1,6>
MV .D1 A4,A0 ; (E) <3,5> Split a long life
|| ADD .S2 1,B4,B4 ; (E) <3,5>
|| MV .L2X A4,B5 ; (E) <3,5> Define a twin register
|| [ A0] STB .D2T2 B5,*-B4(1) ; |80| (E) <2,6>
MV .D1 A4,A0 ; (E) <4,5> Split a long life
|| ADD .S2 1,B4,B4 ; (E) <4,5>
|| MV .L2X A4,B5 ; (E) <4,5> Define a twin register
|| [ A0] STB .D2T2 B5,*-B4(1) ; |80| (E) <3,6>
MV .D1 A4,A0 ; (E) <5,5> Split a long life
|| ADD .S2 1,B4,B4 ; (E) <5,5>
|| MV .L2X A4,B5 ; (E) <5,5> Define a twin register
|| [ A0] STB .D2T2 B5,*-B4(1) ; |80| (E) <4,6>
;** --------------------------------------------------------------------------*
ADD .S2 1,B4,B4 ; (E) <6,5>
|| MV .L2X A4,B5 ; (E) <6,5> Define a twin register
|| MV .D1 A4,A0 ; (E) <6,5> Split a long life
|| [ A0] STB .D2T2 B5,*-B4(1) ; |80| (E) <5,6>
[ A0] STB .D2T2 B5,*-B4(1) ; |80| (E) <6,6>
;** --------------------------------------------------------------------------*
L10:
.line 20
RETNOP .S2 B3,5 ; |85|
; BRANCH OCCURS ; |85|
.endfunc 85,000000000h,0
;******************************************************************************
;* STRINGS *
;******************************************************************************
.sect ".const"
SL1: .string "g_Image0[%d]is %d ",0
SL2: .string "g_Image1[%d]is %d ",0
SL3: .string "g_Image2[%d]is %d",10,0
SL4: .string "g_Image0[%d] is %d ",0
SL5: .string "g_Image1[%d] is %d",10,0
SL6: .string "Error !!!, i = %d, Data0 = %d, Data1 = %d ",10,0
SL7: .string " Good Job, No Error !!!",10,0
;******************************************************************************
;* UNDEFINED EXTERNAL REFERENCES *
;******************************************************************************
.global _printf
.global _rand
.global _srand
.global _time
.global _osd
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
.sym _time_t, 0, 14, 13, 32
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