ti_cc_spi.c

基于CC1100和ATMEGA128的无线通信程序

 	while(MISO_1);
    NOP(); 
    SPI_TX(addr); 
    SPI_TX(value);
    NOP(); 
    SPI_DISABLE(); 
}// TI_CC_SpiWriteReg
//-------------------------------------------------------------------------------------------------------
//  void TI_CC_SpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
// 	写多个寄存器
//  DESCRIPTION:
//      This function writes to multiple CCxxx0 register, using SPI burst access.
//
//  ARGUMENTS:
//      BYTE addr
//          Address of the first CCxxx0 register to be accessed.
//      BYTE *buffer
//          Array of bytes to be written into a corresponding range of
//          CCxx00 registers, starting by the address specified in _addr_.
//      BYTE count
//          Number of bytes to be written to the subsequent CCxxx0 registers.   
//-------------------------------------------------------------------------------------------------------

void TI_CC_SpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count) 
{
    UINT8 i;
    SPI_ENABLE(); 
    while((MISO_1));
    SPI_TX(addr | WRITE_BURST); 
    for (i = 0; i < count; i++) 
    {
    SPI_TX(buffer[i]);
    }
    SPI_DISABLE();
}// TI_CC_SpiWriteBurstReg


 

//-------------------------------------------------------------------------------------------------------
//  void RfWriteRfSettings(RF_SETTINGS *pRfSettings)
// 设置寄存器
//  DESCRIPTION:
//      This function is used to configure the CC2500 based on a given rf setting
//
//  ARGUMENTS:
//      RF_SETTINGS *pRfSettings
//          Pointer to a struct containing rf register settings
//-------------------------------------------------------------------------------------------------------
void TI_CC_RfWriteRfSettings(RF_SETTINGS *pRfSettings) 
{

    // Write register settings
    TI_CC_SpiWriteReg(CCxxx0_FSCTRL1,  pRfSettings->FSCTRL1);
    TI_CC_SpiWriteReg(CCxxx0_FSCTRL0,  pRfSettings->FSCTRL0);
    TI_CC_SpiWriteReg(CCxxx0_FREQ2,    pRfSettings->FREQ2);
    TI_CC_SpiWriteReg(CCxxx0_FREQ1,    pRfSettings->FREQ1);
    TI_CC_SpiWriteReg(CCxxx0_FREQ0,    pRfSettings->FREQ0);
    TI_CC_SpiWriteReg(CCxxx0_MDMCFG4,  pRfSettings->MDMCFG4);
    TI_CC_SpiWriteReg(CCxxx0_MDMCFG3,  pRfSettings->MDMCFG3);
    TI_CC_SpiWriteReg(CCxxx0_MDMCFG2,  pRfSettings->MDMCFG2);
    TI_CC_SpiWriteReg(CCxxx0_MDMCFG1,  pRfSettings->MDMCFG1);
    TI_CC_SpiWriteReg(CCxxx0_MDMCFG0,  pRfSettings->MDMCFG0);
    TI_CC_SpiWriteReg(CCxxx0_CHANNR,   pRfSettings->CHANNR);
    TI_CC_SpiWriteReg(CCxxx0_DEVIATN,  pRfSettings->DEVIATN);
    TI_CC_SpiWriteReg(CCxxx0_FREND1,   pRfSettings->FREND1);
    TI_CC_SpiWriteReg(CCxxx0_FREND0,   pRfSettings->FREND0);
    TI_CC_SpiWriteReg(CCxxx0_MCSM0 ,   pRfSettings->MCSM0 );
    TI_CC_SpiWriteReg(CCxxx0_FOCCFG,   pRfSettings->FOCCFG);
    TI_CC_SpiWriteReg(CCxxx0_BSCFG,    pRfSettings->BSCFG);
    TI_CC_SpiWriteReg(CCxxx0_AGCCTRL2, pRfSettings->AGCCTRL2);
    TI_CC_SpiWriteReg(CCxxx0_AGCCTRL1, pRfSettings->AGCCTRL1);
    TI_CC_SpiWriteReg(CCxxx0_AGCCTRL0, pRfSettings->AGCCTRL0);
    TI_CC_SpiWriteReg(CCxxx0_FSCAL3,   pRfSettings->FSCAL3);
    TI_CC_SpiWriteReg(CCxxx0_FSCAL2,   pRfSettings->FSCAL2);
    TI_CC_SpiWriteReg(CCxxx0_FSCAL1,   pRfSettings->FSCAL1);
    TI_CC_SpiWriteReg(CCxxx0_FSCAL0,   pRfSettings->FSCAL0);
    TI_CC_SpiWriteReg(CCxxx0_FSTEST,   pRfSettings->FSTEST);
    TI_CC_SpiWriteReg(CCxxx0_TEST2,    pRfSettings->TEST2);
    TI_CC_SpiWriteReg(CCxxx0_TEST1,    pRfSettings->TEST1);
    TI_CC_SpiWriteReg(CCxxx0_TEST0,    pRfSettings->TEST0);
    TI_CC_SpiWriteReg(CCxxx0_IOCFG2,   pRfSettings->IOCFG2);
    TI_CC_SpiWriteReg(CCxxx0_IOCFG0,   pRfSettings->IOCFG0);    
    TI_CC_SpiWriteReg(CCxxx0_PKTCTRL1, pRfSettings->PKTCTRL1);
    TI_CC_SpiWriteReg(CCxxx0_PKTCTRL0, pRfSettings->PKTCTRL0);
    TI_CC_SpiWriteReg(CCxxx0_ADDR,     pRfSettings->ADDR);
    TI_CC_SpiWriteReg(CCxxx0_PKTLEN,   pRfSettings->PKTLEN);
    // Set Syn Byte
    TI_CC_SpiWriteReg(CCxxx0_SYNC1,  0x12);
    TI_CC_SpiWriteReg(CCxxx0_SYNC0,  0x34);  
    TI_CC_SpiWriteBurstReg(CCxxx0_PATABLE, paTable, sizeof(paTable));							
}// TI_CC_RfWriteRfSettings



//-------------------------------------------------------------------------------------------------------
//  void TI_CC_RfSendPacket(BYTE *txBuffer, UINT8 size)
//			发送一个数据包
// 最大数据包长度<63; GDO0 设置成监听数据包: TI_CC_SpiWriteReg(CCxxx0_IOCFG0, 0x06);
// 不定长数据包格式,数据包里的第一个字节为数据包长度
//  DESCRIPTION:
//      This function can be used to transmit a packet with packet length up to 63 bytes.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and 
//      de-asserted at the end of the packet => TI_CC_SpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.  
//      
//  ARGUMENTS:
//      BYTE *txBuffer
//          Pointer to a buffer containing the data that are going to be transmitted
//
//      UINT8 size
//          The size of the txBuffer
//-------------------------------------------------------------------------------------------------------


void TI_CC_RfSendPacket(BYTE *txBuffer, UINT8 size) 
{
    //写发送缓冲区
    TI_CC_SpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
    // 进入发送状态
    TI_CC_SpiStrobe(CCxxx0_STX);

    // Wait for GDO0 to be set -> sync transmitted
    //等待同步字节发出
    while (!GDO0_PIN);
    // Wait for GDO0 to be cleared -> end of packet
    //等待数据包发送完毕
    while (GDO0_PIN);
    // Flush RX FIFO; 
    //清接收缓冲区
    TI_CC_SpiStrobe(CCxxx0_SFRX);
    // Flush TX FIFO; 
    //清发送缓冲区
    TI_CC_SpiStrobe(CCxxx0_SFTX);
}// TI_CC_RfSendPacket




//-------------------------------------------------------------------------------------------------------
//  BOOL TI_CC_RfReceivePacket(BYTE *rxBuffer, UINT8 *length)
//		接收一个数据包
// 最大数据包长度<63; GDO0 设置成监听数据包: TI_CC_SpiWriteReg(CCxxx0_IOCFG0, 0x06);
// 不定长数据包格式,数据包里的第一个字节为数据包长度
//  DESCRIPTION: 
//      This function can be used to receive a packet of variable packet length (first byte in the packet
//      must be the length byte). The packet length should not exceed the RX FIFO size.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and 
//      de-asserted at the end of the packet => TI_CC_SpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//      After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
//      are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
//      FIFO is flushed due to address filtering, CRC filtering, or packet length filtering. 
//  
//  ARGUMENTS:
//      BYTE *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      UINT8 *length
//          Pointer to a variable containing the size of the buffer where the incoming data should be
//          stored. After this function returns, that variable holds the packet length.
//          
//  RETURN VALUE:
//      BOOL
//          TRUE:   CRC OK
//          FALSE:  CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
//-------------------------------------------------------------------------------------------------------

BOOL TI_CC_RfReceivePacket(BYTE *rxBuffer, UINT8 length) 
{
    BYTE status[2];
    UINT8 packetLength;
    //进入接收状态
    TI_CC_SpiStrobe(CCxxx0_SRX);
    // Wait for GDO0 to be set -> sync received
    //等待同步字节到来
    while (!GDO0_PIN);
    // Wait for GDO0 to be cleared -> end of packet
    //等待数据包接收完毕
    while (GDO0_PIN);		
    //判断缓冲区里字节数
    if ((TI_CC_SpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) 
    {
			
        // Read length byte
        //读取缓冲区里字节数
        packetLength = TI_CC_SpiReadReg(CCxxx0_RXFIFO);
        // Read data from RX FIFO and store in rxBuffer
        //从接收缓冲区里读取数据
        if (packetLength <= length) 
	   {
            TI_CC_SpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); 

            // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
            //最后两位为数据包完整性校验字节;系统芯片自己加上
            TI_CC_SpiReadBurstReg(CCxxx0_RXFIFO, status, 2); 
            // Flush RX FIFO; 
            //清接收缓冲区
            TI_CC_SpiStrobe(CCxxx0_SFRX);
        		
            // MSB of LQI is the CRC_OK bit
            //回返校验位情况
            return (status[LQI] & CRC_OK);
	   } 
       else{ length = packetLength;
	          // Flush RX FIFO
              //清接收缓冲区
              TI_CC_SpiStrobe(CCxxx0_SFRX);
              return FALSE;}
       } 
       else {return FALSE;}
}// TI_CC_RfReceivePacket