main.lss
来自「基于CC1100和ATMEGA128开发的无线机器人控制程序」· LSS 代码 · 共 1,310 行 · 第 1/4 页
LSS
1,310 行
552: 8e e3 ldi r24, 0x3E ; 62
554: 0e 94 dc 01 call 0x3b8 <halSpiWriteBurstReg>
558: 1f 91 pop r17
55a: 0f 91 pop r16
55c: 08 95 ret
0000055e <halRfSendPacket>:
}// halSpiWriteBurstReg
//-------------------------------------------------------------------------------------------------------
// void halRfSendPacket(BYTE *txBuffer, UINT8 size)
// 发送一个数据包
// 最大数据包长度<63; GDO0 设置成监听数据包: halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// 不定长数据包格式,数据包里的第一个字节为数据包长度
// DESCRIPTION:
// This function can be used to transmit a packet with packet length up to 63 bytes.
// To use this function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
// for it to be cleared.
//
// ARGUMENTS:
// BYTE *txBuffer
// Pointer to a buffer containing the data that are going to be transmitted
//
// UINT8 size
// The size of the txBuffer
//-------------------------------------------------------------------------------------------------------
void halRfSendPacket(BYTE *txBuffer, UINT8 size) {
55e: ff 92 push r15
560: 0f 93 push r16
562: 1f 93 push r17
564: 8c 01 movw r16, r24
566: f6 2e mov r15, r22
//写发送缓冲区
writeln(txBuffer);
568: 0e 94 77 00 call 0xee <writeln>
halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
56c: 4f 2d mov r20, r15
56e: b8 01 movw r22, r16
570: 8f e3 ldi r24, 0x3F ; 63
572: 0e 94 dc 01 call 0x3b8 <halSpiWriteBurstReg>
// 进入发送状态
halSpiStrobe(CCxxx0_STX);
576: 85 e3 ldi r24, 0x35 ; 53
578: 0e 94 c3 01 call 0x386 <halSpiStrobe>
// Wait for GDO0 to be set -> sync transmitted
//等待同步字节发出
while (!GDO0_PIN);
57c: 80 9b sbis 0x10, 0 ; 16
57e: fe cf rjmp .-4 ; 0x57c <halRfSendPacket+0x1e>
// Wait for GDO0 to be cleared -> end of packet
//等待数据包发送完毕
while (GDO0_PIN);
580: 80 99 sbic 0x10, 0 ; 16
582: fe cf rjmp .-4 ; 0x580 <halRfSendPacket+0x22>
584: 1f 91 pop r17
586: 0f 91 pop r16
588: ff 90 pop r15
58a: 08 95 ret
0000058c <halRfReceivePacket>:
}// halRfSendPacket
//-------------------------------------------------------------------------------------------------------
// BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 *length)
// 接收一个数据包
// 最大数据包长度<63; GDO0 设置成监听数据包: halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// 不定长数据包格式,数据包里的第一个字节为数据包长度
// DESCRIPTION:
// This function can be used to receive a packet of variable packet length (first byte in the packet
// must be the length byte). The packet length should not exceed the RX FIFO size.
// To use this function, GD00 must be configured to be asserted when sync word is sent and
// de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
// The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
// for it to be cleared.
// After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
// are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
// FIFO is flushed due to address filtering, CRC filtering, or packet length filtering.
//
// ARGUMENTS:
// BYTE *rxBuffer
// Pointer to the buffer where the incoming data should be stored
// UINT8 *length
// Pointer to a variable containing the size of the buffer where the incoming data should be
// stored. After this function returns, that variable holds the packet length.
//
// RETURN VALUE:
// BOOL
// TRUE: CRC OK
// FALSE: CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
//-------------------------------------------------------------------------------------------------------
BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 length) {
58c: cf 92 push r12
58e: df 92 push r13
590: ef 92 push r14
592: ff 92 push r15
594: 0f 93 push r16
596: 1f 93 push r17
598: cf 93 push r28
59a: df 93 push r29
59c: cd b7 in r28, 0x3d ; 61
59e: de b7 in r29, 0x3e ; 62
5a0: 22 97 sbiw r28, 0x02 ; 2
5a2: 0f b6 in r0, 0x3f ; 63
5a4: f8 94 cli
5a6: de bf out 0x3e, r29 ; 62
5a8: 0f be out 0x3f, r0 ; 63
5aa: cd bf out 0x3d, r28 ; 61
5ac: 6c 01 movw r12, r24
BYTE status[2];
BYTE flag;
UINT8 packetLength;
//进入接收状态
halSpiStrobe(CCxxx0_SRX);
5ae: 84 e3 ldi r24, 0x34 ; 52
5b0: 0e 94 c3 01 call 0x386 <halSpiStrobe>
// Wait for GDO0 to be set -> sync received
//等待同步字节到来
while (!GDO0_PIN);
5b4: 80 9b sbis 0x10, 0 ; 16
5b6: fe cf rjmp .-4 ; 0x5b4 <halRfReceivePacket+0x28>
// Wait for GDO0 to be cleared -> end of packet
//等待数据包接收完毕
while (GDO0_PIN);
5b8: 80 b3 in r24, 0x10 ; 16
5ba: 99 27 eor r25, r25
5bc: 21 e0 ldi r18, 0x01 ; 1
5be: e2 2e mov r14, r18
5c0: f1 2c mov r15, r1
5c2: e8 22 and r14, r24
5c4: f9 22 and r15, r25
5c6: 80 fd sbrc r24, 0
5c8: f7 cf rjmp .-18 ; 0x5b8 <halRfReceivePacket+0x2c>
//判断缓冲区里字节数
if ((halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO))
5ca: 8b e3 ldi r24, 0x3B ; 59
5cc: 0e 94 97 01 call 0x32e <halSpiReadStatus>
5d0: 08 2f mov r16, r24
5d2: 11 27 eor r17, r17
5d4: 0f 77 andi r16, 0x7F ; 127
5d6: 10 70 andi r17, 0x00 ; 0
5d8: 01 15 cp r16, r1
5da: 11 05 cpc r17, r1
5dc: 59 f1 breq .+86 ; 0x634 <halRfReceivePacket+0xa8>
{
writeln("here");
5de: 8d ef ldi r24, 0xFD ; 253
5e0: 91 e0 ldi r25, 0x01 ; 1
5e2: 0e 94 77 00 call 0xee <writeln>
// Read length byte
//读取缓冲区里字节数
packetLength = halSpiReadReg(CCxxx0_RXFIFO);
5e6: 8f e3 ldi r24, 0x3F ; 63
5e8: 0e 94 86 01 call 0x30c <halSpiReadReg>
5ec: 48 2f mov r20, r24
// Read data from RX FIFO and store in rxBuffer
//从接收缓冲区里读取数据
if (packetLength) {
5ee: 88 23 and r24, r24
5f0: c1 f0 breq .+48 ; 0x622 <halRfReceivePacket+0x96>
halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength);
5f2: b6 01 movw r22, r12
5f4: 8f e3 ldi r24, 0x3F ; 63
5f6: 0e 94 a8 01 call 0x350 <halSpiReadBurstReg>
// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
//最后两位为数据包完整性校验字节;系统芯片自己加上
halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2);
5fa: 42 e0 ldi r20, 0x02 ; 2
5fc: be 01 movw r22, r28
5fe: 6f 5f subi r22, 0xFF ; 255
600: 7f 4f sbci r23, 0xFF ; 255
602: 8f e3 ldi r24, 0x3F ; 63
604: 0e 94 a8 01 call 0x350 <halSpiReadBurstReg>
flag=(status[LQI] & CRC_OK);
608: 1a 81 ldd r17, Y+2 ; 0x02
60a: 10 78 andi r17, 0x80 ; 128
if(flag)
60c: 21 f0 breq .+8 ; 0x616 <halRfReceivePacket+0x8a>
{writeln("CRC jiao yan OK!");}
60e: 82 e0 ldi r24, 0x02 ; 2
610: 92 e0 ldi r25, 0x02 ; 2
612: 0e 94 77 00 call 0xee <writeln>
// Flush RX FIFO;
//清接收缓冲区
halSpiStrobe(CCxxx0_SFRX);
616: 8a e3 ldi r24, 0x3A ; 58
618: 0e 94 c3 01 call 0x386 <halSpiStrobe>
// MSB of LQI is the CRC_OK bit
//回返校验位情况
return (flag);
61c: 81 2f mov r24, r17
61e: 99 27 eor r25, r25
620: 0e c0 rjmp .+28 ; 0x63e <halRfReceivePacket+0xb2>
}
else {
// Make sure that the radio is in IDLE state before flushing the FIFO
// (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
// Flush RX FIFO
writeln("error 1");
622: 83 e1 ldi r24, 0x13 ; 19
624: 92 e0 ldi r25, 0x02 ; 2
626: 0e 94 77 00 call 0xee <writeln>
halSpiStrobe(CCxxx0_SFRX);
62a: 8a e3 ldi r24, 0x3A ; 58
62c: 0e 94 c3 01 call 0x386 <halSpiStrobe>
return FALSE; }
630: c7 01 movw r24, r14
632: 05 c0 rjmp .+10 ; 0x63e <halRfReceivePacket+0xb2>
}
else
{ writeln("error 2");
634: 8b e1 ldi r24, 0x1B ; 27
636: 92 e0 ldi r25, 0x02 ; 2
638: 0e 94 77 00 call 0xee <writeln>
return FALSE;
63c: c8 01 movw r24, r16
63e: 22 96 adiw r28, 0x02 ; 2
640: 0f b6 in r0, 0x3f ; 63
642: f8 94 cli
644: de bf out 0x3e, r29 ; 62
646: 0f be out 0x3f, r0 ; 63
648: cd bf out 0x3d, r28 ; 61
64a: df 91 pop r29
64c: cf 91 pop r28
64e: 1f 91 pop r17
650: 0f 91 pop r16
652: ff 90 pop r15
654: ef 90 pop r14
656: df 90 pop r13
658: cf 90 pop r12
65a: 08 95 ret
0000065c <halWait>:
...
}
}// halRfReceivePacket
//-------------------------------------------------------------------------------------------------------
// void halWait(BYTE timeout)
//
// DESCRIPTION:
// Runs an idle loop for [timeout] microseconds.
//
// ARGUMENTS:
// BYTE timeout
// The timeout in microseconds
//-------------------------------------------------------------------------------------------------------
void halWait(BYTE timeout)
{
// This sequence uses exactly 8 clock cycle for each round
do {
NOP();
NOP();
NOP();
NOP();
} while (--timeout);
664: 81 50 subi r24, 0x01 ; 1
666: d1 f7 brne .-12 ; 0x65c <halWait>
668: 08 95 ret
0000066a <__udivmodsi4>:
66a: a1 e2 ldi r26, 0x21 ; 33
66c: 1a 2e mov r1, r26
66e: aa 1b sub r26, r26
670: bb 1b sub r27, r27
672: fd 01 movw r30, r26
674: 0d c0 rjmp .+26 ; 0x690 <__udivmodsi4_ep>
00000676 <__udivmodsi4_loop>:
676: aa 1f adc r26, r26
678: bb 1f adc r27, r27
67a: ee 1f adc r30, r30
67c: ff 1f adc r31, r31
67e: a2 17 cp r26, r18
680: b3 07 cpc r27, r19
682: e4 07 cpc r30, r20
684: f5 07 cpc r31, r21
686: 20 f0 brcs .+8 ; 0x690 <__udivmodsi4_ep>
688: a2 1b sub r26, r18
68a: b3 0b sbc r27, r19
68c: e4 0b sbc r30, r20
68e: f5 0b sbc r31, r21
00000690 <__udivmodsi4_ep>:
690: 66 1f adc r22, r22
692: 77 1f adc r23, r23
694: 88 1f adc r24, r24
696: 99 1f adc r25, r25
698: 1a 94 dec r1
69a: 69 f7 brne .-38 ; 0x676 <__udivmodsi4_loop>
69c: 60 95 com r22
69e: 70 95 com r23
6a0: 80 95 com r24
6a2: 90 95 com r25
6a4: 9b 01 movw r18, r22
6a6: ac 01 movw r20, r24
6a8: bd 01 movw r22, r26
6aa: cf 01 movw r24, r30
6ac: 08 95 ret
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