rf_hal.c

基于CC1100和ATMEGA128开发的无线机器人控制程序

    halSpiWriteReg(CCxxx0_FSTEST,   pRfSettings->FSTEST);
    halSpiWriteReg(CCxxx0_TEST2,    pRfSettings->TEST2);
    halSpiWriteReg(CCxxx0_TEST1,    pRfSettings->TEST1);
    halSpiWriteReg(CCxxx0_TEST0,    pRfSettings->TEST0);
    halSpiWriteReg(CCxxx0_IOCFG2,   pRfSettings->IOCFG2);
    halSpiWriteReg(CCxxx0_IOCFG0,   pRfSettings->IOCFG0);    
    halSpiWriteReg(CCxxx0_PKTCTRL1, pRfSettings->PKTCTRL1);
    halSpiWriteReg(CCxxx0_PKTCTRL0, pRfSettings->PKTCTRL0);
    halSpiWriteReg(CCxxx0_ADDR,     pRfSettings->ADDR);
    halSpiWriteReg(CCxxx0_PKTLEN,   pRfSettings->PKTLEN);
    
    // Set Syn Byte
    halSpiWriteReg(CCxxx0_SYNC1,  0x12);
  	halSpiWriteReg(CCxxx0_SYNC0,  0x34);
    
   	halSpiWriteBurstReg(CCxxx0_PATABLE, paTable, sizeof(paTable));
							
}// halRfWriteRfSettings



//-------------------------------------------------------------------------------------------------------
//  void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count)
// 	写多个寄存器
//  DESCRIPTION:
//      This function writes to multiple CCxxx0 register, using SPI burst access.
//
//  ARGUMENTS:
//      BYTE addr
//          Address of the first CCxxx0 register to be accessed.
//      BYTE *buffer
//          Array of bytes to be written into a corresponding range of
//          CCxx00 registers, starting by the address specified in _addr_.
//      BYTE count
//          Number of bytes to be written to the subsequent CCxxx0 registers.   
//-------------------------------------------------------------------------------------------------------

void halSpiWriteBurstReg(BYTE addr, BYTE *buffer, BYTE count) {
    UINT8 i;
     
    SPI_ENABLE(); 
    while((MISO_1));
    FASTSPI_TX(addr | WRITE_BURST); 
    for (i = 0; i < count; i++) {
         FASTSPI_TX(buffer[i]);
          }
      
    SPI_DISABLE();

}// halSpiWriteBurstReg





//-------------------------------------------------------------------------------------------------------
//  void halRfSendPacket(BYTE *txBuffer, UINT8 size)
//			发送一个数据包
// 最大数据包长度<63; GDO0 设置成监听数据包: halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// 不定长数据包格式,数据包里的第一个字节为数据包长度
//  DESCRIPTION:
//      This function can be used to transmit a packet with packet length up to 63 bytes.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and 
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.  
//      
//  ARGUMENTS:
//      BYTE *txBuffer
//          Pointer to a buffer containing the data that are going to be transmitted
//
//      UINT8 size
//          The size of the txBuffer
//-------------------------------------------------------------------------------------------------------


void halRfSendPacket(BYTE *txBuffer, UINT8 size) {
		//写发送缓冲区
    writeln(txBuffer);
	halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
    // 进入发送状态
    halSpiStrobe(CCxxx0_STX);

   // Wait for GDO0 to be set -> sync transmitted
   //等待同步字节发出
    while (!GDO0_PIN);

    // Wait for GDO0 to be cleared -> end of packet
    //等待数据包发送完毕
    while (GDO0_PIN);
	
   }// halRfSendPacket




//-------------------------------------------------------------------------------------------------------
//  BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 *length)
//		接收一个数据包
// 最大数据包长度<63; GDO0 设置成监听数据包: halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
// 不定长数据包格式,数据包里的第一个字节为数据包长度
//  DESCRIPTION: 
//      This function can be used to receive a packet of variable packet length (first byte in the packet
//      must be the length byte). The packet length should not exceed the RX FIFO size.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and 
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//      After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
//      are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
//      FIFO is flushed due to address filtering, CRC filtering, or packet length filtering. 
//  
//  ARGUMENTS:
//      BYTE *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      UINT8 *length
//          Pointer to a variable containing the size of the buffer where the incoming data should be
//          stored. After this function returns, that variable holds the packet length.
//          
//  RETURN VALUE:
//      BOOL
//          TRUE:   CRC OK
//          FALSE:  CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
//-------------------------------------------------------------------------------------------------------

BOOL halRfReceivePacket(BYTE *rxBuffer, UINT8 length) {
    BYTE status[2];
	BYTE flag;
    UINT8 packetLength;
	//进入接收状态
   	halSpiStrobe(CCxxx0_SRX);
	// Wait for GDO0 to be set -> sync received
    //等待同步字节到来
    while (!GDO0_PIN);
	// Wait for GDO0 to be cleared -> end of packet
    //等待数据包接收完毕
    while (GDO0_PIN);
	
	//判断缓冲区里字节数
		if ((halSpiReadStatus(CCxxx0_RXBYTES) & BYTES_IN_RXFIFO)) 
		{
		writeln("here");
		// Read length byte
        //读取缓冲区里字节数
        packetLength = halSpiReadReg(CCxxx0_RXFIFO);
        // Read data from RX FIFO and store in rxBuffer
        //从接收缓冲区里读取数据
        if (packetLength) {
            halSpiReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength); 
			// Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
            //最后两位为数据包完整性校验字节;系统芯片自己加上
            halSpiReadBurstReg(CCxxx0_RXFIFO, status, 2); 
        	
			flag=(status[LQI] & CRC_OK);
			
			if(flag)
			{writeln("CRC jiao yan OK!");}
			// Flush RX FIFO; 
            //清接收缓冲区
        	halSpiStrobe(CCxxx0_SFRX);
        	// MSB of LQI is the CRC_OK bit
            //回返校验位情况
            return (flag);
        } 
		else {
            // Make sure that the radio is in IDLE state before flushing the FIFO
            // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point) 
            // Flush RX FIFO
           
            writeln("error 1");
            halSpiStrobe(CCxxx0_SFRX);
            return FALSE;   }
               
    
	   } 
	   
	   else
       {  writeln("error 2");
	   return FALSE;
       }
	  
}// halRfReceivePacket


//-------------------------------------------------------------------------------------------------------
//	void halWait(BYTE timeout)
//
//	DESCRIPTION:
//		Runs an idle loop for [timeout] microseconds.
//
//  ARGUMENTS:
//      BYTE timeout
//          The timeout in microseconds
//-------------------------------------------------------------------------------------------------------

void halWait(BYTE timeout)
{
    // This sequence uses exactly 8 clock cycle for each round
    do {
        NOP();
        NOP();
        NOP();
        NOP();
    } while (--timeout);

} // halWait