📄 mcu.h
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/*H**************************************************************************
* NAME: mcu.h
*----------------------------------------------------------------------------
* Copyright (c) 2004 Atmel.
*----------------------------------------------------------------------------
* RELEASE: pwm3-ac-ctrl-motor-0_0_6
* REVISION: 1.6.6.2.2.19
*----------------------------------------------------------------------------
* PURPOSE:
* SFR Description file for Atmegabalast.
*****************************************************************************/
#ifndef MCU_H
#define MCU_H
#define IRQ_MEM_SPACE 2
/*==========================*/
/* Predefined SFR Addresses */
/*==========================*/
/******************************************************************************/
#ifdef __IAR_SYSTEMS_ICC__
/******************************************************************************/
SFR_B(PINB, 0x03) /* Input Pins, Port B */
SFR_B(DDRB, 0x04) /* Data Direction Register, Port B */
SFR_B(PORTB, 0x05) /* Data Register, Port B */
SFR_B(PINC, 0x06) /* Input Pins, Port C */
SFR_B(DDRC, 0x07) /* Data Direction Register, Port C */
SFR_B(PORTC, 0x08) /* Data Register, Port C */
SFR_B(PIND, 0x09) /* Input Pins, Port D */
SFR_B(DDRD, 0x0A) /* Data Direction Register, Port D */
SFR_B(PORTD, 0x0B) /* Data Register, Port D */
SFR_B(PINE, 0x0C) /* Input Pins, Port E */
SFR_B(DDRE, 0x0D) /* Data Direction Register, Port E */
SFR_B(PORTE, 0x0E) /* Data Register, Port E */
SFR_B(TIFR0, 0x15) /* Timer/Counter Interrupt Flag register 0*/
SFR_B(TIFR1, 0x16) /* Timer/Counter Interrupt Flag register 1*/
SFR_B(GPIOR1, 0x19) /* General Purpose Register 1 */
SFR_B(GPIOR2, 0x1A) /* General Purpose Register 2 */
SFR_B(GPIOR3, 0x1B) /* General Purpose Register 3 */
SFR_B(EIFR, 0x1C) /* External Interrupt Flag Register */
SFR_B(EIMSK, 0x1D) /* External Interrupt Mask Register */
SFR_B(GPIOR0, 0x1E) /* General Purpose Register 0 */
SFR_B(EECR, 0x1F) /* EEPROM Control Register */
SFR_B(EEDR, 0x20) /* EEPROM Data Register */
SFR_W(EEAR, 0x21) /* EEPROM Address Register */
SFR_B(GTCCR, 0x23) /* General Purpose Register */
SFR_B(TCCR0A, 0x24) /* Timer/Counter 0 Control Register */
SFR_B(TCCR0B, 0x25) /* Timer/Counter 0 Control Register */
SFR_B(TCNT0, 0x26) /* Timer/Counter 0 */
SFR_B(OCR0A, 0x27) /* Timer/Counter 0 Output Compare Register */
SFR_B(OCR0B, 0x28) /* Timer/Counter 0 Output Compare Register */
SFR_B(PLLCSR, 0x29) /* Pll Control and status register */
SFR_B(SPCR, 0x2C) /* SPI Control Register */
SFR_B(SPSR, 0x2D) /* SPI Status Register */
SFR_B(SPDR, 0x2E) /* SPI I/O Data Register */
SFR_B(ACSR, 0x30) /* Analog Comparator Control and Status Register */
SFR_B(MONDR, 0x31) /* On-Chip Debug Register */
SFR_B(MSMCR, 0x32) /* Monitor stop mode ctrl register */
SFR_B(SMCR, 0x33) /* Sleep Mode Control Register */
SFR_B(MCUSR, 0x34) /* MCU Status Register */
SFR_B(MCUCR, 0x35) /* MCU Control Register */
SFR_B(SPMCSR, 0x37) /* Store Program Memory Control and Status Register */
SFR_W(SP, 0x3D) /* Stack Pointer */
SFR_B(SREG, 0x3F) /* Status Register */
SFR_B_EXT(WDTCSR, 0x60) /* Watchdog Timer Control Register */
SFR_B_EXT(CLKPR, 0x61) /* Clock Prescale Register */
SFR_B_EXT(PRR, 0x64) /* Power Reduction Register */
SFR_B_EXT(OSCCAL, 0x66) /* Oscillator Calibration Register */
SFR_B_EXT(EICRA, 0x69) /* External Interrupt Control Register A */
SFR_B_EXT(TIMSK0, 0x6E) /* Timer/Counter 0 Interrupt Mask Register */
SFR_B_EXT(TIMSK1, 0x6F) /* Timer/Counter 1 Interrupt Mask Register */
SFR_B_EXT(AMP0CSR,0x76) /* Amplifier 0 ctrl and status register */
SFR_B_EXT(AMP1CSR,0x77) /* Amplifier 1 ctrl and status register */
SFR_W_EXT(ADC, 0x78) /* ADC Data register */
SFR_B_EXT(ADCSRA, 0x7A) /* ADC Control and Status Register A */
SFR_B_EXT(ADCSRB, 0x7B) /* ADC Control and Status Register B */
SFR_B_EXT(ADMUX, 0x7C) /* ADC Multiplexer Selection Register */
SFR_B_EXT(DIDR0, 0x7E) /* Digital Input Disable Register 0 */
SFR_B_EXT(DIDR1, 0x7F) /* Digital Input Disable Register 1 */
SFR_B_EXT(TCCR1A, 0x80) /* Timer/Counter 1 Control Register A */
SFR_B_EXT(TCCR1B, 0x81) /* Timer/Counter 1 Control Register B */
SFR_B_EXT(TCCR1C, 0x82) /* Timer/Counter 1 Control Register C */
SFR_W_EXT(TCNT1, 0x84) /* Timer/Counter 1 Register */
SFR_W_EXT(ICR1, 0x86) /* Timer/Counter 1 Input Capture Register */
SFR_W_EXT(OCR1A, 0x88) /* Timer/Counter 1 Output Compare Register A */
SFR_W_EXT(OCR1B, 0x8A) /* Timer/Counter 1 Output Compare Register B */
SFR_B_EXT(PIFR0, 0xA0) /* PSC 0 Interrupt Flag Register */
SFR_B_EXT(PIM0, 0xA1) /* PSC 0 Interrupt Mask Register */
SFR_B_EXT(PIFR1, 0xA2) /* PSC 1 Interrupt Flag Register */
SFR_B_EXT(PIM1, 0xA3) /* PSC 1 Interrupt Mask Register */
SFR_B_EXT(PIFR2, 0xA4) /* PSC 2 Interrupt Flag Register */
SFR_B_EXT(PIM2, 0xA5) /* PSC 2 Interrupt Mask Register */
SFR_B_EXT(DACON, 0xAA) /* DAC Control Register*/
SFR_W_EXT(DAC, 0xAB) /* DAC Data Register*/
SFR_B_EXT(AC0CON, 0xAD) /* Analog Comparator 0 status register */
SFR_B_EXT(AC1CON, 0xAE) /* Analog Comparator 1 status register */
SFR_B_EXT(AC2CON, 0xAF) /* Analog Comparator 2 status register */
SFR_B_EXT(UCSRA, 0xC0) /* USART Control and Status Register A */
SFR_B_EXT(UCSRB, 0xC1) /* USART Control and Status Register B */
SFR_B_EXT(UCSRC, 0xC2) /* USART Control and Status Register C */
SFR_W_EXT(UBRR, 0xC4) /* USART Baud Rate Register Low */
SFR_B_EXT(UDR, 0xC6) /* USART0 I/O Data Register */
/* UCSR0x left for software compatibility*/
SFR_B_EXT(UCSR0A, 0xC0) /* USART Control and Status Register A */
SFR_B_EXT(UCSR0B, 0xC1) /* USART Control and Status Register B */
SFR_B_EXT(UCSR0C, 0xC2) /* USART Control and Status Register C */
SFR_W_EXT(UBRR0, 0xC4) /* USART Baud Rate Register Low */
SFR_B_EXT(UDR0, 0xC6) /* USART0 I/O Data Register */
SFR_B_EXT(EUCSRA, 0xC8) /* EUSART Control and Status Register A */
SFR_B_EXT(EUCSRB, 0xC9) /* EUSART Control and Status Register B */
SFR_B_EXT(EUCSRC, 0xCA) /* EUSART Control and Status Register C */
SFR_W_EXT(MUBRR, 0xCC) /* EUSART Manchester counter max value */
SFR_B_EXT(EUDR, 0xCE) /* USART0 I/O Data Register */
SFR_B_EXT(PSOC0, 0xD0) /* PSC 0 Synchro & Output Configuration */
SFR_W_EXT(OCR0SA, 0xD2) /* PSC 0 Output Compare Register SA */
SFR_W_EXT(OCR0RA, 0xD4) /* PSC 0 Output Compare Register RA */
SFR_W_EXT(OCR0SB, 0xD6) /* PSC 0 Output Compare Register SB */
SFR_W_EXT(OCR0RB, 0xD8) /* PSC 0 Output Compare Register RB */
SFR_B_EXT(PCNF0, 0xDA) /* PSC 0 Configuration Register */
SFR_B_EXT(PCTL0, 0xDB) /* PSC 0 Control Register */
SFR_B_EXT(PFRC0A, 0xDC) /* PSC 0 Input A Control Register */
SFR_B_EXT(PFRC0B, 0xDD) /* PSC 0 Input B Control Register */
SFR_W_EXT(PICR0, 0xDE) /* PSC 0 Input Capture Register */
SFR_B_EXT(PSOC1, 0xE0) /* PSC 1 Synchro & Output Configuration */
SFR_W_EXT(OCR1SA, 0xE2) /* PSC 1 Output Compare Register SA */
SFR_W_EXT(OCR1RA, 0xE4) /* PSC 1 Output Compare Register RA */
SFR_W_EXT(OCR1SB, 0xE6) /* PSC 1 Output Compare Register SB */
SFR_W_EXT(OCR1RB, 0xE8) /* PSC 1 Output Compare Register RB */
SFR_B_EXT(PCNF1, 0xEA) /* PSC 1 Configuration Register */
SFR_B_EXT(PCTL1, 0xEB) /* PSC 1 Control Register */
SFR_B_EXT(PFRC1A, 0xEC) /* PSC 1 Input A Control Register */
SFR_B_EXT(PFRC1B, 0xED) /* PSC 1 Input B Control Register */
SFR_W_EXT(PICR1, 0xEE) /* PSC 1 Input Capture Register */
SFR_B_EXT(PSOC2, 0xF0) /* PSC 2 Synchro & Output Configuration */
SFR_B_EXT(POM2, 0xF1) /* PSC 2 Output Matrix Register */
SFR_W_EXT(OCR2SA, 0xF2) /* PSC 2 Output Compare Register SA */
SFR_W_EXT(OCR2RA, 0xF4) /* PSC 2 Output Compare Register RA */
SFR_W_EXT(OCR2SB, 0xF6) /* PSC 2 Output Compare Register SB */
SFR_W_EXT(OCR2RB, 0xF8) /* PSC 2 Output Compare Register RB */
SFR_B_EXT(PCNF2, 0xFA) /* PSC 2 Configuration Register */
SFR_B_EXT(PCTL2, 0xFB) /* PSC 2 Control Register */
SFR_B_EXT(PFRC2A, 0xFC) /* PSC 2 Input A Control Register */
SFR_B_EXT(PFRC2B, 0xFD) /* PSC 2 Input B Control Register */
SFR_W_EXT(PICR2, 0xFE) /* PSC 2 Input Capture Register */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
/* NB! vectors are specified as byte addresses */
#define RESET_vect (0x00*IRQ_MEM_SPACE)
#define PSC2_CAPT_vect (0x01*IRQ_MEM_SPACE)
#define PSC2EC_vect (0x02*IRQ_MEM_SPACE)
#define PSC1_CAPT_vect (0x03*IRQ_MEM_SPACE)
#define PSC1EC_vect (0x04*IRQ_MEM_SPACE)
#define PSC0_CAPT_vect (0x05*IRQ_MEM_SPACE)
#define PSC0EC_vect (0x06*IRQ_MEM_SPACE)
#define ANACOMP_0_vect (0x07*IRQ_MEM_SPACE)
#define ANACOMP_1_vect (0x08*IRQ_MEM_SPACE)
#define ANACOMP_2_vect (0x09*IRQ_MEM_SPACE)
#define INT0_vect (0x0A*IRQ_MEM_SPACE)
#define TIMER1_CAPT_vect (0x0B*IRQ_MEM_SPACE)
#define TIMER1_COMPA_vect (0x0C*IRQ_MEM_SPACE)
#define TIMER1_COMPB_vect (0x0D*IRQ_MEM_SPACE)
#define TIMER1_OVF_vect (0x0F*IRQ_MEM_SPACE)
#define TIMER0_COMPA_vect (0x10*IRQ_MEM_SPACE)
#define TIMER0_OVF_vect (0x11*IRQ_MEM_SPACE)
#define ADC_vect (0x12*IRQ_MEM_SPACE)
#define INT1_vect (0x13*IRQ_MEM_SPACE)
#define SPI_STC_vect (0x14*IRQ_MEM_SPACE)
#define USART_RXC_vect (0x15*IRQ_MEM_SPACE)
#define USART_UDRE_vect (0x16*IRQ_MEM_SPACE)
#define USART_TXC_vect (0x17*IRQ_MEM_SPACE)
#define INT2_vect (0x18*IRQ_MEM_SPACE)
#define WDT_vect (0x19*IRQ_MEM_SPACE)
#define EE_RDY_vect (0x1A*IRQ_MEM_SPACE)
#define TIMER0_COMPB_vect (0x1B*IRQ_MEM_SPACE)
#define INT3_vect (0x1C*IRQ_MEM_SPACE)
#define SPM_READY_vect (0x1F*IRQ_MEM_SPACE)
#endif /* _IAR_ */
/******************************************************************************/
#ifdef _ICC_
/******************************************************************************/
#define PINB (*(volatile unsigned char *)0x23) /* Input Pins, Port B */
#define DDRB (*(volatile unsigned char *)0x24) /* Data Direction Register, Port B */
#define PORTB (*(volatile unsigned char *)0x25) /* Data Register, Port B */
#define PINC (*(volatile unsigned char *)0x26) /* Input Pins, Port C */
#define DDRC (*(volatile unsigned char *)0x27) /* Data Direction Register, Port C */
#define PORTC (*(volatile unsigned char *)0x28) /* Data Register, Port C */
#define PIND (*(volatile unsigned char *)0x29) /* Input Pins, Port D */
#define DDRD (*(volatile unsigned char *)0x2A) /* Data Direction Register, Port D */
#define PORTD (*(volatile unsigned char *)0x2B) /* Data Register, Port D */
#define PINE (*(volatile unsigned char *)0x2C) /* Input Pins, Port E */
#define DDRE (*(volatile unsigned char *)0x2D) /* Data Direction Register, Port E */
#define PORTE (*(volatile unsigned char *)0x2E) /* Data Register, Port E */
#define TIFR0 (*(volatile unsigned char *)0x35) /* Timer/Counter Interrupt Flag register 0*/
#define TIFR1 (*(volatile unsigned char *)0x36) /* Timer/Counter Interrupt Flag register 1*/
#define GPIOR1 (*(volatile unsigned char *)0x39) /* General Purpose Register 1 */
#define GPIOR2 (*(volatile unsigned char *)0x3A) /* General Purpose Register 2 */
#define GPIOR3 (*(volatile unsigned char *)0x3B) /* General Purpose Register 3 */
#define EIFR (*(volatile unsigned char *)0x3C) /* External Interrupt Flag Register */
#define EIMSK (*(volatile unsigned char *)0x3D) /* External Interrupt Mask Register */
#define GPIOR0 (*(volatile unsigned char *)0x3E) /* General Purpose Register 0 */
#define EECR (*(volatile unsigned char *)0x3F) /* EEPROM Control Register */
#define EEDR (*(volatile unsigned char *)0x40) /* EEPROM Data Register */
#define EEAR (*(volatile unsigned int *)0x41) /* EEPROM Address Register */
#define GTCCR (*(volatile unsigned char *)0x43) /* General Purpose Register */
#define TCCR0A (*(volatile unsigned char *)0x44) /* Timer/Counter 0 Control Register */
#define TCCR0B (*(volatile unsigned char *)0x45) /* Timer/Counter 0 Control Register */
#define TCNT0 (*(volatile unsigned char *)0x46) /* Timer/Counter 0 */
#define OCR0A (*(volatile unsigned char *)0x47) /* Timer/Counter 0 Output Compare Register */
#define OCR0B (*(volatile unsigned char *)0x48) /* Timer/Counter 0 Output Compare Register */
#define PLLCSR (*(volatile unsigned char *)0x49) /* Pll control and status Register */
#define SPCR (*(volatile unsigned char *)0x4C) /* SPI Control Register */
#define SPSR (*(volatile unsigned char *)0x4D) /* SPI Status Register */
#define SPDR (*(volatile unsigned char *)0x4E) /* SPI I/O Data Register */
#define ACSR (*(volatile unsigned char *)0x50) /* Analog Comparator Control and Status Register */
#define MONDR (*(volatile unsigned char *)0x51) /* On-Chip Debug Register */
#define MSMDR (*(volatile unsigned char *)0x52) /* Monitor Stop mode control Register */
#define SMCR (*(volatile unsigned char *)0x53) /* Sleep Mode Control Register */
#define MCUSR (*(volatile unsigned char *)0x54) /* MCU Status Register */
#define MCUCR (*(volatile unsigned char *)0x55) /* MCU Control Register */
#define SPMCSR (*(volatile unsigned char *)0x57) /* Store Program Memory Control and Status Register */
#define SP (*(volatile unsigned int *)0x5D) /* Stack Pointer */
#define SREG (*(volatile unsigned char *)0x5F) /* Status Register */
#define WDTCSR (*(volatile unsigned char *)0x60) /* Watchdog Timer Control Register */
#define CLKPR (*(volatile unsigned char *)0x61) /* Clock Prescale Register */
#define PRR (*(volatile unsigned char *)0x64) /* Power Reduction Register */
#define OSCCAL (*(volatile unsigned char *)0x66) /* Oscillator Calibration Register */
#define EICRA (*(volatile unsigned char *)0x69) /* External Interrupt Control Register A */
#define TIMSK0 (*(volatile unsigned char *)0x6E) /* Timer/Counter 0 Interrupt Mask Register */
#define TIMSK1 (*(volatile unsigned char *)0x6F) /* Timer/Counter 1 Interrupt Mask Register */
#define AMP0CSR (*(volatile unsigned int *)0x76) /* Amplifier0 ctrl and status register */
#define AMP1CSR (*(volatile unsigned char *)0x77) /* Amplifier1 ctrl and status register */
#define ADC (*(volatile unsigned int *)0x78) /* ADC Data register */
#define ADCL (*(volatile unsigned char *)0x78) /* ADC Data register */
#define ADCH (*(volatile unsigned char *)0x79) /* ADC Data register */
#define ADCSRA (*(volatile unsigned char *)0x7A) /* ADC Control and Status Register A */
#define ADCSRB (*(volatile unsigned char *)0x7B) /* ADC Control and Status Register B */
#define ADMUX (*(volatile unsigned char *)0x7C) /* ADC Multiplexer Selection Register */
#define DIDR0 (*(volatile unsigned char *)0x7E) /* Digital Input Disable Register 0 */
#define DIDR1 (*(volatile unsigned char *)0x7F) /* Digital Input Disable Register 1 */
#define TCCR1A (*(volatile unsigned char *)0x80) /* Timer/Counter 1 Control Register A */
#define TCCR1B (*(volatile unsigned char *)0x81) /* Timer/Counter 1 Control Register B */
#define TCCR1C (*(volatile unsigned char *)0x82) /* Timer/Counter 1 Control Register C */
#define TCNT1 (*(volatile unsigned int *)0x84) /* Timer/Counter 1 Register */
#define ICR1 (*(volatile unsigned int *)0x86) /* Timer/Counter 1 Input Capture Register */
#define OCR1A (*(volatile unsigned int *)0x88) /* Timer/Counter 1 Output Compare Register A */
#define OCR1AL (*(volatile unsigned char *)0x88) /* Timer/Counter 1 Output Compare Register A */
#define OCR1AH (*(volatile unsigned char *)0x89) /* Timer/Counter 1 Output Compare Register A */
#define OCR1B (*(volatile unsigned int *)0x8A) /* Timer/Counter 1 Output Compare Register B */
#define PIFR0 (*(volatile unsigned char *)0xA0) /* PSC0 interrupt flag Register */
#define PIM0 (*(volatile unsigned char *)0xA1) /* PSC 0 interrupt mask Register */
#define PIFR1 (*(volatile unsigned char *)0xA2) /* PSC1 interrupt flag Register */
#define PIM1 (*(volatile unsigned char *)0xA3) /* PSC 1 interrupt mask Register */
#define PIFR2 (*(volatile unsigned char *)0xA4) /* PSC2 interrupt flag Register */
#define PIM2 (*(volatile unsigned char *)0xA5) /* PSC 2 interrupt mask Register */
#define DACON (*(volatile unsigned char *)0xAA) /* DAC Control Register */
#define DAC (*(volatile unsigned int *)0xAB) /* DAC data Register */
#define DACL (*(volatile unsigned char *)0xAB) /* DAC data Register */
#define DACH (*(volatile unsigned char *)0xAC) /* DAC data Register */
#define AC0CON (*(volatile unsigned char *)0xAD) /* Analog Comparator 0 status register */
#define AC1CON (*(volatile unsigned char *)0xAE) /* Analog Comparator 1 status register */
#define AC2CON (*(volatile unsigned char *)0xAF) /* Analog Comparator 2 status register */
#define UCSRA (*(volatile unsigned char *)0xC0) /* USART Control and Status Register A */
#define UCSRB (*(volatile unsigned char *)0xC1) /* USART Control and Status Register B */
#define UCSRC (*(volatile unsigned char *)0xC2) /* USART Control and Status Register C */
#define UBRR (*(volatile unsigned int *)0xC4) /* USART Baud Rate Register */
#define UBRRL (*(volatile unsigned char *)0xC4) /* USART Baud Rate Register Low */
#define UBRRH (*(volatile unsigned char *)0xC5) /* USART Baud Rate Register High */
#define UDR (*(volatile unsigned char *)0xC6) /* USART I/O Data Register */
/*USART0 left for compatibility*/
#define UCSR0A (*(volatile unsigned char *)0xC0) /* USART0 Control and Status Register A */
#define UCSR0B (*(volatile unsigned char *)0xC1) /* USART0 Control and Status Register B */
#define UCSR0C (*(volatile unsigned char *)0xC2) /* USART0 Control and Status Register C */
#define UBRR0 (*(volatile unsigned int *)0xC4) /* USART0 Baud Rate Register */
#define UBRR0L (*(volatile unsigned char *)0xC4) /* USART0 Baud Rate Register Low */
#define UBRR0H (*(volatile unsigned char *)0xC5) /* USART0 Baud Rate Register High */
#define UDR0 (*(volatile unsigned char *)0xC6) /* USART0 I/O Data Register */
/*EUSART */
#define EUCSRA (*(volatile unsigned char *)0xC8) /* EUSART Control and Status Register A */
#define EUCSRB (*(volatile unsigned char *)0xC9) /* EUSART Control and Status Register B */
#define EUCSRC (*(volatile unsigned char *)0xCA) /* EUSART Control and Status Register C */
#define MUBRR (*(volatile unsigned int *)0xCC) /* EUSART Max manchester receiver counter */
#define MUBRRL (*(volatile unsigned char *)0xCC) /* EUSART Max manchester receiver counter */
#define MUBRRH (*(volatile unsigned char *)0xCD) /* EUSART Max manchester receiver counter */
#define EUDR (*(volatile unsigned char *)0xCE) /* USART0 I/O Data Register */
#define PSOC0 (*(volatile unsigned char *)0xD0) /* PSC 0 Synchro & Output Configuration */
#define OCR0SA (*(volatile unsigned int *)0xD2) /* PSC 0 Output Compare Register SA */
#define OCR0SAL (*(volatile unsigned char *)0xD2) /* PSC 0 Output Compare Register SA */
#define OCR0SAH (*(volatile unsigned char *)0xD3) /* PSC 0 Output Compare Register SA */
#define OCR0RA (*(volatile unsigned int *)0xD4) /* PSC 0 Output Compare Register RA*/
#define OCR0RAL (*(volatile unsigned char *)0xD4) /* PSC 0 Output Compare Register RA*/
#define OCR0RAH (*(volatile unsigned char *)0xD5) /* PSC 0 Output Compare Register RA*/
#define OCR0SB (*(volatile unsigned int *)0xD6) /* PSC 0 Output Compare Register SB */
#define OCR0SBL (*(volatile unsigned char *)0xD6) /* PSC 0 Output Compare Register SB */
#define OCR0SBH (*(volatile unsigned char *)0xD7) /* PSC 0 Output Compare Register SB */
#define OCR0RB (*(volatile unsigned int*)0xD8) /* PSC 0 Output Compare Register RB */
#define OCR0RBL (*(volatile unsigned char*)0xD8) /* PSC 0 Output Compare Register RB */
#define OCR0RBH (*(volatile unsigned char*)0xD9) /* PSC 0 Output Compare Register RB */
#define PCNF0 (*(volatile unsigned char *)0xDA) /* PSC 0 Configuration Register */
#define PCTL0 (*(volatile unsigned char *)0xDB) /* PSC 0 Control Register */
#define PFRC0A (*(volatile unsigned char *)0xDC) /* PSC 0 Input A Control Register */
#define PFRC0B (*(volatile unsigned char *)0xDD) /* PSC 0 Input B Control Register */
#define PICR0 (*(volatile unsigned int *)0xDE) /* PSC 0 Input Capture Register */
#define PSOC1 (*(volatile unsigned char *)0xE0) /* PSC 1 Synchro & Output Configuration */
#define OCR1SA (*(volatile unsigned int *)0xE2) /* PSC 1 Output Compare Register SA */
#define OCR1SAL (*(volatile unsigned char *)0xE2) /* PSC 1 Output Compare Register SA */
#define OCR1SAH (*(volatile unsigned char *)0xE3) /* PSC 1 Output Compare Register SA */
#define OCR1RA (*(volatile unsigned int *)0xE4) /* PSC 1 Output Compare Register RA*/
#define OCR1RAL (*(volatile unsigned char *)0xE4) /* PSC 1 Output Compare Register RA*/
#define OCR1RAH (*(volatile unsigned char *)0xE5) /* PSC 1 Output Compare Register RA*/
#define OCR1SB (*(volatile unsigned int *)0xE6) /* PSC 1 Output Compare Register SB */
#define OCR1SBL (*(volatile unsigned char *)0xE6) /* PSC 1 Output Compare Register SB */
#define OCR1SBH (*(volatile unsigned char *)0xE7) /* PSC 1 Output Compare Register SB */
#define OCR1RB (*(volatile unsigned int*)0xE8) /* PSC 1 Output Compare Register RB */
#define OCR1RBL (*(volatile unsigned char*)0xE8) /* PSC 1 Output Compare Register RB */
#define OCR1RBH (*(volatile unsigned char*)0xE9) /* PSC 1 Output Compare Register RB */
#define PCNF1 (*(volatile unsigned char *)0xEA) /* PSC 1 Configuration Register */
#define PCTL1 (*(volatile unsigned char *)0xEB) /* PSC 1 Control Register */
#define PFRC1A (*(volatile unsigned char *)0xEC) /* PSC 1 Input A Control Register */
#define PFRC1B (*(volatile unsigned char *)0xED) /* PSC 1 Input B Control Register */
#define PICR1 (*(volatile unsigned int *)0xEE) /* PSC 1 Input Capture Register */
#define PSOC2 (*(volatile unsigned char *)0xF0) /* PSC 2 Synchro & Output Configuration */
#define OCR2SA (*(volatile unsigned int *)0xF2) /* PSC 2 Output Compare Register SA */
#define OCR2SAL (*(volatile unsigned char *)0xF2) /* PSC 2 Output Compare Register SA */
#define OCR2SAH (*(volatile unsigned char *)0xF3) /* PSC 2 Output Compare Register SA */
#define OCR2RA (*(volatile unsigned int *)0xF4) /* PSC 2 Output Compare Register RA*/
#define OCR2RAL (*(volatile unsigned char *)0xF4) /* PSC 2 Output Compare Register RA*/
#define OCR2RAH (*(volatile unsigned char *)0xF5) /* PSC 2 Output Compare Register RA*/
#define OCR2SB (*(volatile unsigned int *)0xF6) /* PSC 2 Output Compare Register SB */
#define OCR2SBL (*(volatile unsigned char *)0xF6) /* PSC 2 Output Compare Register SB */
#define OCR2SBH (*(volatile unsigned char *)0xF7) /* PSC 2 Output Compare Register SB */
#define OCR2RB (*(volatile unsigned int*)0xF8) /* PSC 2 Output Compare Register RB */
#define OCR2RBL (*(volatile unsigned char*)0xF8) /* PSC 2 Output Compare Register RB */
#define OCR2RBH (*(volatile unsigned char*)0xF9) /* PSC 2 Output Compare Register RB */
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