📄 tl16c550c.inc
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**********************************************************************************
*THIS FILE FOR TL16C550C ASYNCHRONOUS COMMUNICATION ELEMENT
*WRITED BY BaiYangong
*DATA: 1/30/2005
*********************************************************************************
.bss count,1
.bss count1,1
.bss count2,1
.bss count3,1
.bss LCR,1
.bss DLSB,1
.bss DMSB,1
.bss FCR,1
.bss IER,1
.bss RBR,1
.bss THR,1
.bss IIR,1
.bss LSR,1
.bss MCR,1
***************************************************************
;使用TL16C550时，首先是进行初始化，包括写LCR寄存器的BIT7后写DLSB和DMSB，
;然后写LCR寄存器来设置数据字长、奇偶校验、停止位和波特率，
;然后写FCR来设置FIFO的深度，再写IER设置中断使能寄存器和读LSR对其清零。
;初始化后，就可读RBR，写THR来实现数据的传输了。
***************************************************************
INIT_TL16C550 .macro
LD #03H,A ;禁止访问DLSB、DMSB
STL A,@LCR
PORTW LCR,0003H
RPT #30
NOP
LD #00h,A ;禁止tl16c550中断
STL A,@IER
PORTW IER,0001H
RPT #30
NOP
LD #83H,A ;串行字符字长8位，
STL A,@LCR ;1个停止位，无校验，
PORTW LCR,0003H ;禁止断开控制，
RPT #30 ;可以访问DLSB、DMSB
NOP
LD #06H,A ;波特率为9600
STL A,@DLSB
PORTW DLSB,0000H
RPT #30
NOP
LD #00H,A
STL A,@DMSB
PORTW DMSB,0001H
RPT #30
NOP
LD #03H,A ;禁止访问DLSB、DMSB
STL A,@LCR
PORTW LCR,0003H
RPT #30
NOP
;LD #07H,A ;使能并清零发送接收器，深度为8字节
;STL A,@FCR
;PORTW FCR,0002H
;RPT #30
;NOP
LD #01H,A ;使能中断
STL A,@IER
PORTW IER,0001H
RPT #30
NOP
NOP
.endm
;address of TL16C550 register
;RBR -> 0x4000 ; read
;THR -> 0x4000 ; write
;IER -> 0x4001
;IIR -> 0x4002
;FCR -> 0x4002
;LCR -> 0x4003
;MCR -> 0x4004
;LSR -> 0x4005
;MSR -> 0x4006
;SCR -> 0x4007
;DLSB -> 0x4000
;DMSB -> 0x4001
;Register Selection Table
;-------------------------------------------------------------------------------------
; DLAB | A2 | A1 | A0 | Registers |
; 0 | 0 | 0 | 0 | Rceciver Buffer(Read) , Transmitter holding register(write) |
; 0 | 0 | 0 | 1 | Interrupt enable register |
; x | 0 | 1 | 0 | Interrupt Identification register(Read only) |
; x | 0 | 1 | 0 | FIFO control register (write) |
; x | 0 | 1 | 1 | Line Control register |
; x | 1 | 0 | 0 | Modem control register |
; x | 1 | 0 | 1 | Line sratus register |
; x | 1 | 1 | 0 | Modem status register |
; x | 1 | 1 | 1 | Scratch register |
; 1 | 0 | 0 | 0 | Divisor latch(LSB) |
; 1 | 0 | 0 | 1 | Divesor latch(MSB) |
*-------------------------------------------------------------------------------------
;FIFO control register(FCR)
TL_FCR_UNUSE .set 00000000b<<8 ;unuse bits
TL_FCR_TREL .set 00b<<6 ;trigger level
;--------------------------------------------------------
; bit7 | bit6 | receiver FIFO trigger level(BYTES) |
; 0 | 0 | 01 |
; 0 | 1 | 04 |
; 1 | 0 | 08 |
; 1 | 1 | 14 |
;---------------------------------------------------------
TL_FCR_RSE .set 00b<<4 ;Reserved bits
TL_FCR_DMA .set 0b<<3 ;when FCR0 is set ,setting FCR3 causes RXRDY and TXRDY to change from level 0 to 1
TL_FCR_CLST .set 0b<<2 ;when set ,clears all bytes in the transmit FIFO and clears its counter
TL_FCR_CLSR .set 0b<<1 ;when set ,clears all bytes in the receiver FIFO and clears its counter
TL_FCR_EABF .set 0b<<0 ;when set ,enable the transmitter and receiver FIFOs ,change this bits clears the FIFOs
TL_FCR .set TL_FCR_UNUSE | TL_FCR_TREL | TL_FCR_RSE | TL_FCR_DMA | TL_FCR_CLST | TL_FCR_CLSR | TL_FCR_EABF
;FCR0=1 && IER0=1 && IER2=1 enable reeiver FIFO and receiver interrupts
;the receiver line status interrupt (IIR-6) has higher priority than the receiver data available(IIR-4)interrupt
;the data ready bit(LSR0)is set when a character is transferred from the shift register to the receiver FIFO,it is cleared when the FIFO is empty
;FIFO time-out intrerupt occurs if the following conditions exist:
;a At least one character is in the FIFO
;b the most recent serial character was received more than four continuous character times ago
;c the most recent microprocessor read of the FIFO has occurred more than four continuous character times before ,this cause o maximum character received command to interrupt an issued delay
TL_IER_UNUSE .set 00000000b<<8 ;unused bits
TL_IER_RSE .set 0000b<<4 ;Reserved bits
TL_IER_MSI .set 0b<<3 ;modem status interrupt
TL_IER_RLSI .set 1b<<2 ;receiver line status interrupt
TL_IER_THRE .set 1b<<1 ;THRE interrupt
TL_IER_REDA .set 1b<<0 ;receiver data available
TL_IER .set TL_IER_UNUSE | TL_IER_RSE | TL_IER_MSI | TL_IER_RLSI | TL_IER_THRE | TL_IER_REDA
;IIR
;LCR
TL_LCR_UNUSE .set 00000000b<<8 ;unused bits
TL_LCR_DLAB .set 0b<<7 ;divisor latch access bit
TL_LCR_BREAK .set 0b<<6 ;break control bit enable
TL_LCR_STICK .set 0b<<5 ;when LCR3=LCR4-LCR5=1 , parity bit is transmitted and checked as cleared
;when LCR3=LCR5=1,LCR4=0.parity bit is transmitted and checked an set
TL_LCR_EVEN_ODD .set 1b<<4 ;this bit is the even parity select bit . when parity is enabled and bit4 is set even parity is selected
TL_LCR_PARITY .set 1b<<3 ;this bit is the parity enable bit
TL_LCR_STOP .set 0b<<2 ;when bit2 is cleared , one stop bit is generated in the data , when bit2 is set ,the number of stop bits
;generated is dependent on the word length selected with bit 0 and 1
;-----------------------------------------------
; bit2 | word_length | number of stop bits |
; 0 | any | 1 |
; 1 | 5 | 1.5 |
; 1 | 6 | 2 |
; 1 | 7 | 2 |
; 1 | 8 | 2 |
;-----------------------------------------------
TL_LCR_WORD_LEN .set 11b<<0 ;word length
;---------------------------
; bit1 | bit0 | word_length |
; 0 | 0 | 5 |
; 0 | 1 | 6 |
; 1 | 0 | 7 |
; 1 | 1 | 8 |
;---------------------------
TL_LCR .set TL_LCR_UNUSE | TL_LCR_DLAB | TL_LCR_BREAK | TL_LCR_STICK | TL_LCR_EVEN_ODD | TL_LCR_PARITY | TL_LCR_STOP | TL_LCR_WORD_LEN
;LSR bits definition
;bit0 :receiver data ready
;bit1 overrun error
;bit2 parity error
;bit3 framing error
;bit4 break interrupt
;bit5 THRE indicator ,THRE is set when the THR is empty , indicating that the ACE is ready to accept a new character
;bit6 TEMT bit is set when the THR and TSR are both empty ⌨️ 快捷键说明
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