cmos035tech.lef

MP3解码的ASIC全部过程

#******
# FILE: "cmos035tech.lef"
#
# 04-FEB-2000, Herman Witters (IMEC)
#   New file.
#
# 14-JUN-2000, Herman Witters (IMEC)
#   Added ANTENNAAREAFACTOR values.
#
# 31-JUL-2000, Herman Witters (IMEC)
#   Added default PINANTENNASIZE values.
#   Added ANTENNAAREAFACTOR values.  The antenna check doesn't seem to
#   flag all possible antenna's, but it will flag the worst ones.
#******

#******
# Note: Routing capacitance extraction
# ************************************
# Author: Herman Witters (IMEC)
#
# Because of the limitations of the extraction of routing capacitance
# in Silicon Ensemble, some approximations have been made to obtain
# extraction results that probably are worst case, but not "too" worst
# case either.
# Only typical values have been given because derating factors are
# usually applied by the analysis tools (simulators, critical path
# analyzers, ...).
#
# Symbols used:
#
#   Ca{layer_spec}    = area capacitance
#   Cs{layer_spec}    = side capacitance (fringe or coupling)
#   layer_spec        = layer or layers considered for capacitance
#
# Metal1 routing is only done between cells so the only capacitance
# to consider is metal1-well capacitance.
#
#   Ca{m1} = Ca{m1-well}
#
#   Cs{m1} = Cs{m1-well}
#
# Metal2 routing runs in the vertical direction and crosses metal1
# wires (from a cell or routing) that have minimal width and spacing.
# The capacitance is proportionally divided over the metal2-metal1
# and metal2-well overlap using the minimal width and spacing of
# metal1.
#
#   %: metal1 routing
#   @: metal2 routing
#
#                  @@@    @@@
#   width{m1} / %%%@@@%%%%@@@%%%                 \
#             \ %%%@@@%%%%@@@%%%                  | track =
#                  @@@    @@@    \ spacing{m1-m1} | width + spacing
#                  @@@    @@@    /               /
#               %%%@@@%%%%@@@%%%
#               %%%@@@%%%%@@@%%%
#                  @@@    @@@
#
#   Ca{m2} = (width{m1} * Ca{m2-m1} + spacing{m1-m1} * Ca{m2-well})
#            / (width{m1} + spacing{m1-m1})
#
#   Cs{m2} = (width{m1} * Cs{m2-m1} + spacing{m1-m1} * Cs{m2-well})
#            / (width{m1} + spacing{m1-m1})
#
# Metal3 routing runs in the horizontal direction and crosses metal2
# wires that have minimal width and spacing.
# In between the metal2 wires, the metal3 routing runs over metal1
# wires (from a cell or routing).
# The capacitance is proportionally divided over the metal3-metal2
# and metal3-metal1 overlap using the minimal width and spacing of
# metal2.
#
#   @: metal2 routing
#   &: metal3 routing
#       _
#      / \width{m2}
#      @@@    @@@
#   &&&&&&&&&&&&&&&&
#   &&&&&&&&&&&&&&&&
#      @@@    @@@
#      @@@    @@@
#   &&&&&&&&&&&&&&&&
#   &&&&&&&&&&&&&&&&
#      @@@    @@@
#         \__/ spacing{m2-m2}
#      \_____/
#             track = width + spacing
#
#   Ca{m3} = (width{m2} * Ca{m3-m2} + spacing{m2-m2} * Ca{m3-m1})
#            / (width{m2} + spacing{m2-m2})
#
#   Cs{m3} = (width{m2} * Cs{m3-m2} + spacing{m2-m2} * Cs{m3-m1})
#            / (width{m2} + spacing{m2-m2})
#
# For metal4, routing on metal3 and metal2 is considered and
# for metal5, routing on metal4 and metal3.
#
# When there are multiple values for Cs in the datasheet, the
# worst case value is used.  This is usual the coupling capacitance
# in case of adjacent lines.
#
# Values used for Ca and Cs calculations are based on document:
#
#   Alcatel Microelectronics
#   C035M-D design rule manual
#   DS13330, revision 02, 01-02-1999
#******

VERSION 5.1 ;

NAMESCASESENSITIVE ON ;

BUSBITCHARS "<>" ;

UNITS
    DATABASE MICRONS 1000 ;
END UNITS

# INPUTPINANTENNASIZE defaults to input pin of IV cell.
INPUTPINANTENNASIZE    1.4 ;
OUTPUTPINANTENNASIZE   0.0 ;
INOUTPINANTENNASIZE    0.0 ;

LAYER poly
    TYPE MASTERSLICE ;
END poly

LAYER contact
    TYPE CUT ;
    SPACING 0.50 ;
END contact

LAYER metal1
    TYPE ROUTING ;
    WIDTH 0.500 ;
    SPACING 0.600 ;
    PITCH 1.500 ;
    DIRECTION HORIZONTAL ;
    RESISTANCE RPERSQ 0.072 ;
    CAPACITANCE CPERSQDIST 2.38e-05 ;
    EDGECAPACITANCE 6.71e-05 ;
    ANTENNAAREAFACTOR 0.00334 ;
END metal1

LAYER v1
    TYPE CUT ;
    SPACING 0.50 ;
END v1

LAYER metal2
    TYPE ROUTING ;
    WIDTH 0.700 ;
    SPACING 0.700 ;
    PITCH 1.500 ;
    DIRECTION VERTICAL ;
    RESISTANCE RPERSQ 0.055 ;
    CAPACITANCE CPERSQDIST 2.384e-05 ;
    EDGECAPACITANCE 6.733e-05 ;
    ANTENNAAREAFACTOR 0.00334 ;
END metal2

LAYER v2
    TYPE CUT ;
    SPACING 0.50 ;
END v2

LAYER metal3
    TYPE ROUTING ;
    WIDTH 0.700 ;
    SPACING 0.700 ;
    PITCH 1.500 ;
    DIRECTION HORIZONTAL ;
    RESISTANCE RPERSQ 0.055 ;
    CAPACITANCE CPERSQDIST 2.605e-05 ;
    EDGECAPACITANCE 6.705e-05 ;
    ANTENNAAREAFACTOR 0.00334 ;
END metal3

LAYER v3
    TYPE CUT ;
    SPACING 0.50 ;
END v3

LAYER metal4
    TYPE ROUTING ;
    WIDTH 0.700 ;
    SPACING 0.700 ;
    PITCH 1.500 ;
    DIRECTION VERTICAL ;
    RESISTANCE RPERSQ 0.055 ;
    CAPACITANCE CPERSQDIST 2.605e-05 ;
    EDGECAPACITANCE 6.705e-05 ;
    ANTENNAAREAFACTOR 0.00334 ;
END metal4

LAYER v4
    TYPE CUT ;
    SPACING 0.50 ;
END v4

LAYER metal5
    TYPE ROUTING ;
    WIDTH 0.800 ;
    SPACING 2.000 ;
    PITCH 3.000 ;
    DIRECTION HORIZONTAL ;
    RESISTANCE RPERSQ 0.035 ;
    CAPACITANCE CPERSQDIST 2.605e-05 ;
    EDGECAPACITANCE 4.695e-05 ;
    ANTENNAAREAFACTOR 0.00334 ;
END metal5

VIA M2_M1 DEFAULT
    RESISTANCE 1.500 ;
    LAYER metal1 ;
        RECT -0.350 -0.350 0.350 0.350 ;
    LAYER v1 ;
        RECT -0.200 -0.200 0.200 0.200 ;
    LAYER metal2 ;
        RECT -0.350 -0.350 0.350 0.350 ;
END M2_M1

VIA M3_M2 DEFAULT
    RESISTANCE 1.500 ;
    LAYER metal2 ;
        RECT -0.350 -0.350 0.350 0.350 ;
    LAYER v2 ;
        RECT -0.200 -0.200 0.200 0.200 ;
    LAYER metal3 ;
        RECT -0.350 -0.350 0.350 0.350 ;
END M3_M2

VIA M4_M3 DEFAULT
    RESISTANCE 1.500 ;
    LAYER metal3 ;
        RECT -0.350 -0.350 0.350 0.350 ;
    LAYER v3 ;
        RECT -0.200 -0.200 0.200 0.200 ;
    LAYER metal4 ;
        RECT -0.350 -0.350 0.350 0.350 ;
END M4_M3

VIA M5_M4 DEFAULT
    RESISTANCE 1.500 ;
    LAYER metal4 ;
        RECT -0.350 -0.350 0.350 0.350 ;
    LAYER v4 ;
        RECT -0.200 -0.200 0.200 0.200 ;
    LAYER metal5 ;
        RECT -0.400 -0.400 0.400 0.400 ;
END M5_M4

VIARULE M2_M1_G GENERATE
    LAYER metal1 ;
        DIRECTION HORIZONTAL ;
        OVERHANG 0.150 ;
        METALOVERHANG 0.000 ;
    LAYER metal2 ;
        DIRECTION VERTICAL ;
        OVERHANG 0.150 ;
        METALOVERHANG 0.000 ;
    LAYER v1 ;
        RECT -0.200 -0.200 0.200 0.200 ;
        SPACING 0.900 BY 0.900 ;
END M2_M1_G

VIARULE M3_M2_G GENERATE
    LAYER metal2 ;
        DIRECTION VERTICAL ;
        OVERHANG 0.150 ;
        METALOVERHANG 0.000 ;
    LAYER metal3 ;
        DIRECTION HORIZONTAL ;
        OVERHANG 0.150 ;
        METALOVERHANG 0.000 ;
    LAYER v2 ;
        RECT -0.200 -0.200 0.200 0.200 ;
        SPACING 0.900 BY 0.900 ;
END M3_M2_G

VIARULE M4_M3_G GENERATE
    LAYER metal3 ;
        DIRECTION HORIZONTAL ;
        OVERHANG 0.150 ;
        METALOVERHANG 0.000 ;
    LAYER metal4 ;
        DIRECTION VERTICAL ;
        OVERHANG 0.150 ;
        METALOVERHANG 0.000 ;
    LAYER v3 ;
        RECT -0.200 -0.200 0.200 0.200 ;
        SPACING 0.900 BY 0.900 ;
END M4_M3_G

VIARULE M5_M4_G GENERATE
    LAYER metal4 ;
        DIRECTION VERTICAL ;
        # Used 0.2 micron instead of 0.15 because the power router
        # does not generate enough overhang for metal5 otherwise.
        OVERHANG 0.200 ;
        METALOVERHANG 0.000 ;
    LAYER metal5 ;
        DIRECTION HORIZONTAL ;
        OVERHANG 0.200 ;
        METALOVERHANG 0.000 ;
    LAYER v4 ;
        RECT -0.200 -0.200 0.200 0.200 ;
        SPACING 0.900 BY 0.900 ;
END M5_M4_G

VIARULE TURN1 GENERATE
    LAYER metal1 ;
        DIRECTION horizontal ;
    LAYER metal1 ;
        DIRECTION vertical ;
END TURN1

VIARULE TURN2 GENERATE
    LAYER metal2 ;
        DIRECTION vertical ;
    LAYER metal2 ;
        DIRECTION horizontal ;
END TURN2

VIARULE TURN3 GENERATE
    LAYER metal3 ;
        DIRECTION horizontal ;
    LAYER metal3 ;
        DIRECTION vertical ;
END TURN3

VIARULE TURN4 GENERATE
    LAYER metal4 ;
        DIRECTION vertical ;
    LAYER metal4 ;
        DIRECTION horizontal ;
END TURN4

VIARULE TURN5 GENERATE
    LAYER metal5 ;
        DIRECTION horizontal ;
    LAYER metal5 ;
        DIRECTION vertical ;
END TURN5

SPACING
    SAMENET contact contact 0.500 ;
    SAMENET metal1 metal1 0.600 ;
    SAMENET v1 v1 0.500 ;
    SAMENET metal2 metal2 0.700 STACK ;
    SAMENET v1 v2 0.000 STACK ;
    SAMENET v2 v2 0.500 STACK ;
    SAMENET metal3 metal3 0.700 STACK ;
    SAMENET v2 v3 0.000 STACK ;
    SAMENET v3 v3 0.500 STACK ;
    SAMENET metal4 metal4 0.700 STACK ;
    SAMENET v3 v4 0.000 STACK ;
    SAMENET v4 v4 0.500 ;
    SAMENET metal5 metal5 2.000 ;
END SPACING

END LIBRARY