regs840x.h

神龙解压卡Linux下的完整开发包,绝对是超值超值超值

/*****************************************************************************
*  regs840x.h : registers common for EM840X and EM847X
*  REALmagic Quasar Hardware Library
*  Created by Aurelia Popa-Radu
*  Copyright Sigma Designs Inc
*  Sigma Designs Proprietary and confidential
*  Created on 8/7/01
*  Description:
*****************************************************************************/

#ifndef __REGS840X_H__
#define __REGS840X_H__

// defines PCI registers
#define QPM_master_xfer_enable		0x1FE3

#define QPM_from_host_addr_lo		0x1FE0
#define QPM_from_host_addr_hi		0x1FE1
#define QPM_from_host_xfer_cnt		0x1FE2
#define QPM_xfer_reverse			0x1FE4

// defines audio-serial registers
#define AUDIO_bytecnt_lo			0x1FD0
#define AUDIO_bytecnt_hi			0x1FD1
#define AUDIO_bytecnt_trig_lo		0x1FD2
#define AUDIO_bytecnt_trig_hi		0x1FD3
#define AUDIO_sync_state			0x1FD4
#define AUDIO_serial_ctrl0			0x1FD5
#define AUDIO_serial_ctrl1			0x1FD6
#define AUDIO_serial_gain			0x1FD7
#define AUDIO_spdif_chstat0			0x1FD8
#define AUDIO_spdif_chstat1			0x1FD9
#define AUDIO_in_counter			0x1FDB

// defines J1 registers
#define AUDIO_ac3_status_lo			0x1FC0
#define AUDIO_ac3_status_hi			0x1FC1
#define AUDIO_ac3_cop				0x1FC2
#define AUDIO_ac3_mode				0x1FC3
#define AUDIO_ac3_romaddrsel		0x1FC4
#define AUDIO_ac3_romdatalo			0x1FC5
#define AUDIO_ac3_romdatahi			0x1FC6

// defines J1 DM registers
#define AUDIO_CmDmOsConf			0x19C0
#define AUDIO_HLDynRange			0x19C1
#define AUDIO_RepeatCnt				0x19C2
#define AUDIO_HLPcmScale			0x19C3

// defines audio-pcm registers
#define AUDIO_pcm_mix0				0x1FB0
#define AUDIO_pcm_mix1				0x1FB1
#define AUDIO_pcm_mix2				0x1FB2
#define AUDIO_pcm_mix3				0x1FB3
#define AUDIO_pcm_mix4				0x1FB4
#define AUDIO_pcm_mix5				0x1FB5
#define AUDIO_pcm_mix6				0x1FB6
#define AUDIO_pcm_mix7				0x1FB7
#define AUDIO_pcm_invert			0x1FB8
#define AUDIO_pcm_config0			0x1FB9
#define AUDIO_pcm_config1			0x1FBA

#define VID_HORZ_TOTAL				0x1F42
#define VID_HSYNC_WIDTH				0x1F43
#define VID_VERT_TOTAL				0x1F44
#define VID_VSYNC_WIDTH				0x1F45
#define VID_VSYNC_FINE_ADJ			0x1F46
#define VID_TOP_FIELD_HEIGHT		0x1F48
#define VID_TOP_FIELD_START			0x1F49
#define VID_BOT_FIELD_START			0x1F4A
#define VID_CTRL1					0x1F5E
#define VID_CTRL2					0x1F47
#define VID_CTRL3					0x1F5F

// defines TV registers
#define SIGMATV_CONFIG				0x1F30
#define SIGMATV_HSYNC_PERIOD		0x1F31
#define SIGMATV_HSYNC_0				0x1F32
#define SIGMATV_HSYNC_1				0x1F33
#define SIGMATV_VSYNC_PERIOD		0x1F34
#define SIGMATV_VSYNC_ODD_LINE_0	0x1F35
#define SIGMATV_VSYNC_ODD_PIXEL_0	0x1F36
#define SIGMATV_VSYNC_ODD_LINE_1	0x1F37
#define SIGMATV_VSYNC_ODD_PIXEL_1	0x1F38
#define SIGMATV_VSYNC_EVEN_LINE_0	0x1F39
#define SIGMATV_VSYNC_EVEN_PIXEL_0	0x1F3A
#define SIGMATV_VSYNC_EVEN_LINE_1	0x1F3B
#define SIGMATV_VSYNC_EVEN_PIXEL_1	0x1F3C
#define SIGMATV_CC_DATA				0x1F3D
// end new defines Quasar3

//Display Controller
#define VID_Y_BCS					0x1F40
#define VID_C_BCS					0x1F41
#define VID_HSYNC_LO				0x1F42
#define VID_HSYNC_HI				0x1F43
#define VID_VSYNC_LO				0x1F44
#define VID_VSYNC_HI				0x1F45
#define VID_VSYNC_DLY				0x1F46
#define VID_CTRLX					0x1F47
#define VID_Y_MPEGLINE				0x1F48
#define VID_C_MPEGLINE				0x1F49
#define VID_SCAN_LINE				0x1F4A
#define VID_SCAN_MAX				0x1F4B

#define PIO_DATA_Q1					0x1F4E	// for Quasar1
#define PIO_DIR_Q1					0x1F4F	// for Quasar1
#define PIO_DATA_Q2					0x1F4D	// for Quasar2...
#define PIO_DIR_Q2					0x1F4E	// for Quasar2...

#define VID_MPEGWIDTH				0x1F53
#define VID_MPEGHEIGHT				0x1F54
#define VID_DISCARD					0x1F55
#define VID_HDS_SCALE				0x1F56
#define VID_VUS_SCALE				0x1F57
#define VID_HUS_SCALE				0x1F58
#define VID_US_PHASE				0x1F59
#define VID_WIN_TOP					0x1F5A
#define VID_WIN_BOT					0x1F5B
#define VID_WIN_LEFT				0x1F5C
#define VID_WIN_RIGHT				0x1F5D
#define VID_CTRL					0x1F5E
#define VID_IRQ						0x1F5F
#define SP_COLOR					0x1F60
#define SP_CONTRAST					0x1F61
#define SP_HOFFSET					0x1F62
#define SP_VOFFSET					0x1F63
#define SP_WIDTH					0x1F64
#define SP_HEIGHT					0x1F65
#define SP_HCROP_WIDTH				0x1F66
#define SP_VDS_SCALE				0x1F67
#define SP_HDS_SCALE				0x1F68
#define SP_VUS_SCALE				0x1F69
#define SP_HUS_SCALE				0x1F6A
#define SP_WIN_TOP					0x1F6B
#define SP_WIN_BOT					0x1F6C
#define SP_WIN_LEFT					0x1F6D
#define SP_WIN_RIGHT				0x1F6E
#define SP_CTRL						0x1F6F
#define BTN_COLOR					0x1F70
#define BTN_CONTRAST				0x1F71
#define BTN_WIN_TOP					0x1F72
#define BTN_WIN_BOT					0x1F73
#define BTN_WIN_LEFT				0x1F74
#define BTN_WIN_RIGHT				0x1F75
#define SP_CLUT_Y0					0x1F80
#define SP_CLUT_C0					0x1F81

#define VID_VLD_WIN_TOP				0x1f4F
#define VID_VLD_WIN_BOT				0x1F50
#define VID_VLD_WIN_LEFT			0x1F51
#define VID_VLD_WIN_RIGHT			0x1F52

#define OSD_WIDTH					0x1FA0
#define OSD_HEIGHT					0x1FA1
#define OSD_TOP						0x1FA2
#define OSD_BOT						0x1FA3
#define OSD_LEFT					0x1FA4
#define OSD_RIGHT					0x1FA5
#define OSD_HLT						0x1FA6
#define OSD_HLB						0x1FA7
#define OSD_HLL						0x1FA8
#define OSD_HLR						0x1FA9
#define OSD_VSCALE					0x1FAA
#define OSD_HSCALE					0x1FAB
#define OSD_PHASE					0x1FAC
#define OSD_CTRL					0x1FAD
#define OSD_CLUT_ADDR				0x1FAE
#define OSD_CLUT_DATA				0x1FAF

#define RISC_mode_w					0x1FF0
#define RISC_length_w				0x1FF1
#define RISC_address_w				0x1FF2
#define RISC_loopback				0x1FF3
#define RISC_mode_r					0x1FF4
#define RISC_length_r				0x1FF5
#define RISC_address_r				0x1FF6
#define RISC_resets_0				0x1FF8
#define RISC_resets_1				0x1FF9
#define RISC_irq					0x1FFA
#define RISC_tim_div				0x1FFB
#define RISC_tim_cnt				0x1FFC

#endif