instructions_ppc.c

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}

/*
 * ------------------------------------------
 * mtsrin OEA supervisor Form X
 * 	Move to segment register indirect
 * incomplete v1
 * ------------------------------------------
 */
void 
i_mtsrin(uint32_t icode) {
	/*  OEA Supervisor */
	int s = (icode>>21)&0x1f;
	int b = (icode>>11)&0x1f;	
	SR(GPR(b)>>28) = GPR(s);
	fprintf(stderr,"instr i_mtsrin(%08x) not implemented\n",icode);
}

/*
 *-----------------------------------------------------------
 * dcbtst VEA Form X
 * 	Data Block touch for store
 *	Currently ignored because no cache is emulated
 * v1
 *-----------------------------------------------------------
 */
void 
i_dcbtst(uint32_t icode) {
	int a = (icode>>16) & 0x1f;
	int b = (icode>>21) & 0x1f;
	uint32_t ea;
	if(a) {
		ea = GPR(a) + GPR(b);
	} else {
		ea = GPR(b);
	}
	fprintf(stderr,"ignore i_dcbtst(%08x)\n",icode);
}

/*
 * ----------------------------------
 * stbux UISA Form X
 *  	Store byte with update indexed
 * v1
 * ----------------------------------
 */
void 
i_stbux(uint32_t icode) {
	int s = (icode>>21)&0x1f;
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;	
	uint32_t ea;
	ea = GPR(a) + GPR(b);
	MMU_Write8(GPR(s)&0xff,ea);
	GPR(a) = ea;
	fprintf(stderr,"instr i_stbux(%08x)\n",icode);
}

/*
 * ----------------------------------
 * ADDx UISA Form XO 
 * v1
 * ----------------------------------
 */
void 
i_addx(uint32_t icode) {
	int d = (icode>>21)&0x1f;	
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	int oe = icode&(1<<10);
	int rc = icode&1;
	uint32_t result,op1,op2;
	op1=GPR(a); op2 = GPR(b); 		
	GPR(d) = result = op1+op2;
	if(oe) {
		if(add_overflow( op1,op2,result)) {
			XER |= XER_SO | XER_OV;
    		} else {
			XER &= ~XER_OV;
    		}
	}
	if(rc) {
		update_cr0(result);
	}
	dprintf("instr i_addx(%08x)\n",icode);
}

/*
 * ---------------------------------------
 * dcbt VEA Form X
 * 	Data block touch
 * v1
 * ---------------------------------------
 */
void 
i_dcbt(uint32_t icode) {
	int a = (icode>>16) & 0x1f;
	int b = (icode>>21) & 0x1f;
	uint32_t ea;
	if(a) {
		ea = GPR(a) + GPR(b);
	} else {
		ea = GPR(b);
	}
	fprintf(stderr,"ignore i_dcbt(%08x) not implemented\n",icode);
}

/*
 * --------------------------------------
 * lhzx UISA Form X
 * 	Load half word and Zero indexed
 * v1
 * --------------------------------------
 */
void 
i_lhzx(uint32_t icode) {
	int d = (icode>>21)&0x1f;
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	uint32_t ea;
	if(a==0) {
		ea=GPR(b);
	} else {
		ea=GPR(a)+GPR(b);
	}
	GPR(d) = MMU_Read16(ea);
	fprintf(stderr,"instr i_lhzx(%08x)\n",icode);
}

/*
 * ---------------------------------
 * eqvx  UISA Form X
 * v1
 * ---------------------------------
 */
void 
i_eqvx(uint32_t icode) {
	int s=(icode>>21)&0x1f;
	int a=(icode>>16)&0x1f;
	int b=(icode>>10)&0x1f;
	int rc=icode&1;
	uint32_t result;
	result = GPR(a) = ~(GPR(s) ^ GPR(b));
	if(rc) {
		update_cr0(result);
	}
	fprintf(stderr,"instr i_eqvx(%08x)\n",icode);
}

/*
 * ------------------------------------------------------
 * tlbie OEA supervisor optional Form X
 * Translation Lookaside Buffer invalidate Entry
 * Currently invalidates all
 * ------------------------------------------------------
 */
void 
i_tlbie(uint32_t icode) {
	MMU_InvalidateTlb();
	fprintf(stderr,"instr i_tlbie(%08x)\n",icode);
}

/*
 * ------------------------------------------
 * eciwx
 * incomplete v1
 * ------------------------------------------
 */
void 
i_eciwx(uint32_t icode) {
	int d = (icode>>21) & 0x1f;
	int a = (icode>>16) & 0x1f;
	int b = (icode>>11) & 0x1f;
	uint32_t ea;	
	if(!(EAR & (1<<31))) {
		/* Exception */
		fprintf(stderr,"DSI Exception missing here\n");
		return;
	}
	if(a==0) {
		ea = GPR(b);
	} else {
		ea = GPR(a) + GPR(b);
	}
	GPR(d) = MMU_Read32(ea); /* Nocache */
	fprintf(stderr,"instr i_eciwx(%08x) not implemented\n",icode);
}

/*
 * ------------------------------------------------
 * lhzux UISA Form X
 * Load half word and zero with update indexed
 * ------------------------------------------------
 */
void 
i_lhzux(uint32_t icode) {
	int d = (icode>>21)&0x1f;
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	uint32_t ea;
	ea=GPR(a)+GPR(b);
	GPR(d) = MMU_Read16(ea);
	GPR(a)=ea;
	fprintf(stderr,"instr i_lhzux(%08x) not implemented\n",icode);
}

/*
 * --------------------------------------------------
 * xorx  UISA Form X
 * 	XOR
 * --------------------------------------------------
 */
void 
i_xorx(uint32_t icode) {
	int s = (icode>>21)&0x1f;
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	int rc = icode & 1;
	uint32_t result;
	result = GPR(a) = GPR(s) ^ GPR(b);	
	if(rc) {
		update_cr0(result);	
	}
	dprintf("instr i_xorx(%08x)\n",icode);
}

/*
 * ------------------------------------------------------------------
 * mfspr
 * incomplete v1
 * ------------------------------------------------------------------
 */
void 
i_mfspr(uint32_t icode) {
	int d = (icode>>21)&0x1f;
	int n = (((icode>>16)&0x1f)) | (((icode>>11)&0x1f)<<5);
	/* Check for Supervisor here ! */
	int oea = 1; 
	if(oea || (n==1) || (n==8)|| (n==9)) {
		if(HAS_SPR(n)) {
			GPR(d) = SPR(n);	
		} else if (HAS_SPR_READ(n)) {
			GPR(d) = SPR_READ(n);
		} else {
			/* Illegal instruction type or undefined */
			fprintf(stderr,"Mist, nonexisting SPR %d\n",n);
		}
	} else {
		fprintf(stderr,"Mist, illegal mfspr %d icode %d\n",n,icode);
	}	
	fprintf(stderr,"instr i_mfspr(%08x)\n",icode);
}

void 
i_lwax(uint32_t icode) {
	fprintf(stderr,"instr i_lwax(%08x) not implemented\n",icode);
}

/*
 * ------------------------------------------------
 * lhax UISA Form X
 *	Load Half word algebraic indexed	
 * v1
 * ------------------------------------------------
 */
void 
i_lhax(uint32_t icode) {
	int d=(icode>>21)&0x1f;
	int a=(icode>>16)&0x1f;
	int b=(icode>>11)&0x1f;
	uint32_t ea;
	uint32_t result;
	if(a==0) {
		ea=GPR(b);
	} else {
		ea = GPR(a) + GPR(b);
	}
	result=MMU_Read16(ea);
	if(result&0x8000) {	
		GPR(d) = result|0xffff0000;
	} else {
		GPR(d)=result;
	}
	fprintf(stderr,"instr i_lhax(%08x)\n",icode);
}

/*
 * ----------------------------------------------------
 * tlbia OEA supervisor optional Form X
 * 	Translation Lookaside Buffer invalidate all
 * ----------------------------------------------------
 */
void 
i_tlbia(uint32_t icode) {
	MMU_InvalidateTlb();
	fprintf(stderr,"instr i_tlbia(%08x)\n",icode);
}

/*
 * ----------------------------------------------------------------------
 * mftb
 * move from timebase
 *
 * ----------------------------------------------------------------------
 */
void 
i_mftb(uint32_t icode) {
	/* VEA */
	int d = (icode>>21)&0x1f;
	int n = (((icode>>16)&0x1f)) | (((icode>>11)&0x1f)<<5);
	if(n==268) {
		GPR(d) = TBL;
	} else if (n==269) {
		GPR(d) = TBU;
	} else {
		fprintf(stderr,"Illegal time base register\n");
		// Exception illegal instruction
	}
	fprintf(stderr,"instr i_mftb(%08x)\n",icode);
}

void 
i_lwaux(uint32_t icode) {
	fprintf(stderr,"instr i_lwaux(%08x) not implemented\n",icode);
}

/*
 * -------------------------------------------------------
 * lhaux UISA Form X
 * 	Load half word algebraic with update indexed
 * v1
 * -------------------------------------------------------
 */
void 
i_lhaux(uint32_t icode) {
	int d=(icode>>21)&0x1f;
	int a=(icode>>16)&0x1f;
	int b=(icode>>11)&0x1f;
	uint32_t ea;
	uint32_t result;
	if((a==0)||(a==d)) {
		fprintf(stderr,"Illegal instruction format\n");
		return;
	} 
	ea = GPR(a) + GPR(b);
	result=MMU_Read16(ea);
	if(result&0x8000) {	
		GPR(d) = result|0xffff0000;
	} else {
		GPR(d)=result;
	}
	GPR(a)=ea;
	fprintf(stderr,"instr i_lhaux(%08x) not implemented\n",icode);
}

/*
 * --------------------------------
 * sthx UISA Form X
 * 	Store Half Word Indexed
 * v1
 * --------------------------------
 */
void 
i_sthx(uint32_t icode) {
	int s=(icode >> 21)&0x1f;
	int a=(icode >> 16)&0x1f;
	int b=(icode >> 11)&0x1f;
	uint32_t ea;
	if(a) {
		ea = GPR(a) + GPR(b);
	} else {
		ea = GPR(b);
	}
	MMU_Write16(GPR(s)&0xffff,ea);
	fprintf(stderr,"instr i_sthx(%08x)\n",icode);
}

/*
 * ----------------------------------------
 * orcx UISA Form X
 * OR with complement
 * ----------------------------------------
 */
void 
i_orcx(uint32_t icode) {
	int s = (icode>>21) & 0x1f;
	int a = (icode>>16) & 0x1f;
	int b = (icode>>11) & 0x1f;
	int rc = icode & 1;
	uint32_t result;
	result = GPR(a) = GPR(s) | ~GPR(b);
	if(rc) {
		update_cr0(result);
	}
	fprintf(stderr,"instr i_orcx(%08x)\n",icode);
}

void 
i_slbie(uint32_t icode) {
	fprintf(stderr,"instr i_slbie(%08x) not implemented\n",icode);
}

/*
 * ----------------------------------------------
 * ecowx 
 * External Control word out indexed
 * incomplete v1
 * ----------------------------------------------
 */
void 
i_ecowx(uint32_t icode) {
	int s = (icode>>21) & 0x1f;
	int a = (icode>>16) & 0x1f;
	int b = (icode>>11) & 0x1f;
	uint32_t ea;	
	if(!(EAR & (1<<31))) {
		fprintf(stderr,"exception missing here\n");
		return;
	}
	if(a==0) {
		ea = GPR(b);
	} else {
		ea = GPR(a) + GPR(b);
	}
	if(ea&3) {
		fprintf(stderr,"Alignment exception missing here\n");
		return;
	}
	MMU_Write32(GPR(s),ea); /* nochache */
	fprintf(stderr,"instr i_ecowx(%08x)\n",icode);
}

/*
 * ---------------------------------------------------------
 * sthux  UISA Form X
 * Store Half word with Update Indexed
 * v1
 * ---------------------------------------------------------
 */
void 
i_sthux(uint32_t icode) {
	int s=(icode >> 21)&0x1f;
	int a=(icode >> 16)&0x1f;
	int b=(icode >> 11)&0x1f;
	uint32_t ea;
	ea = GPR(a) + GPR(b);
	MMU_Write16(GPR(s)&0xffff,ea);
	GPR(a) = ea;
	fprintf(stderr,"instr i_sthux(%08x)\n",icode);
}

/*
 * --------------------------------
 * orx UISA Form X 
 * v1
 * --------------------------------
 */
void 
i_orx(uint32_t icode) {
	uint32_t result;
	int s=(icode >> 21)&0x1f;
	int a=(icode >> 16)&0x1f;
	int b=(icode >> 11)&0x1f;
	int rc=icode&1;
	result = GPR(a) = GPR(s) | GPR(b);
	if(rc) {
		update_cr0(result);
	}
	fprintf(stderr,"instr i_orx(%08x) at %08x\n",icode,CIA);
}

void 
i_divdux(uint32_t icode) {
	fprintf(stderr,"instr i_divdux(%08x) not implemented\n",icode);
}

/*
 * --------------------------------
 * divwux UISA Form XO
 * v1
 * --------------------------------
 */
void 
i_divwux(uint32_t icode) {
	int d = (icode>>21)&0x1f;
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	int oe =  (icode>>10)&1;
	int rc =  icode&1;
	uint32_t result;
	if(GPR(b)) {
		result =  GPR(a)/GPR(b);
	} else {
		fprintf(stderr,"Warning undefined result of division\n");
		result = 47110815; /* undefined */
	}
	if(oe) {
		XER=XER & ~XER_OV;
		if(GPR(b)==0) {
			XER |= XER_OV | XER_SO;
		}
	}
	if(rc) {
		update_cr0(result);
	}
	GPR(d) = result;
	fprintf(stderr,"instr i_divwux(%08x)\n",icode);
}

/*
 * ----------------------------------------------
 * mtspr UISA/OEA sometimes supervisor form XFX 
 * 	Move to special purpose register
 * incomplete v1
 * ----------------------------------------------
 */
/*
	mtxer rD equivalent to mtspr 1,rD
	mtlr rD  equivalent to mtspr 8,rD
	mtctr rD equivalent to mtspr 9,rD
*/
void 
i_mtspr(uint32_t icode) {
	int s = (icode>>21)&0x1f;
	int n = (((icode>>16)&0x1f)) | (((icode>>11)&0x1f)<<5);
	/* Check for OEA here ! */
	int supervisor = 1; 
	if(supervisor || (n==1) || (n==8)|| (n==9)) {
		if(HAS_SPR(n)) {
			SPR(n) = GPR(s);	
			fprintf(stderr,"mtspr: SPR %d new value %08x from R%d\n",n,GPR(s),s);
		} else if (HAS_SPR_WRITE(n)) {
			SPR_WRITE(GPR(s),n);
		} else {
			fprintf(stderr,"mtspr: Mist, SPR %d does not exist, icode %08x\n",n,icode);
		}
		if(n==9) {
			fprintf(stderr,"Load spr(9) with %08x\n",GPR(s));
		}
	} else {
		fprintf(stderr,"Mist, mtspr not allowed %08x\n",icode);
#if 0	
		Exception();
#endif
		return;
	}	
	dprintf("instr i_mtspr(%08x) not implemented\n",icode);
}

/*
 * -------------------------------------------------------
 * dcbi VEA Form X 
 *	Data Cache Block Invalidate
 *	Is ignored because no data cache is emulated
 * v1
 * --------------------------------------------------------
 */
void 
i_dcbi(uint32_t icode) {
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	uint32_t ea;
	if(a) {
		ea = GPR(a) + GPR(b);
	} else {
		ea = GPR(b);
	}
#if 0
	if(!translate_address(ea))  {
		PPC_Exception(DSI);
	}
#endif
	fprintf(stderr,"ignore i_dcbi(%08x)\n",icode);
}

/*
 * ---------------------------------------------------
 * nandx UISA Form X
 * 	NAND
 * v1
 * ---------------------------------------------------
 */
void 
i_nandx(uint32_t icode) {
	int s = (icode>>21)&0x1f;	
	int a = (icode>>16)&0x1f;	
	int b = (icode>>11)&0x1f;	
	int rc = icode & 1;
	uint32_t result;
	result = GPR(a) = ~(GPR(s) & GPR(b));
	if(rc) {
		update_cr0(result);
	}
	fprintf(stderr,"instr i_nandx(%08x) not implemented\n",icode);
}

void 
i_divdx(uint32_t icode) {
	fprintf(stderr,"instr i_divdx(%08x) not implemented\n",icode);
}

/*
 * ------------------------------------
 * divwx UISA Form XO
 * v1
 * ------------------------------------
 */
void 
i_divwx(uint32_t icode) {
	int d = (icode>>21)&0x1f;
	int a = (icode>>16)&0x1f;
	int b = (icode>>11)&0x1f;
	int oe =  (icode>>10)&1;
	int rc =  icode&1;
	int32_t result;
	if(GPR(b)) {
		result = (int32_t)GPR(a)/(int32_t)GPR(b);
	} else {
		fprintf(stderr,"Warning undefined result of division\n");
		result = 0x47110815; /* Manual says undefined */
	}
	if(oe) {
		XER=XER & ~XER_OV;
		if((GPR(a)==0x80000000) && (GPR(b)==0xffffffff)) {
			XER |= XER_OV | XER_SO;
		}
		if(GPR(b)==0) {
			XER |= XER_OV | XER_SO;
		}
	}
	if(rc) {
		update_cr0(result);
	}
	GPR(d) = result;
	fprintf(stderr,"instr i_divwx(%08x) not implemented\n",icode);
}

void 
i_slbia(uint32_t icode) {
	fprintf(stderr,"instr i_slbia(%08x) not implemented\n",icode);