skyeye_mach_s3c44b0x.c

skyeye_1_2_2_Rel.rar 最新skyeye源码

					s3c44b0x_update_int(state);
				}
			}
			break;

		case UBRDIV0:
			io.ubrdiv0 = data;
			break;
		case UBRDIV1:
			io.ubrdiv1 = data;
			break;

		default:
			break;
	}
}


/* Timer Routine */
static int s3c44b0x_timer_check_state(int timer_index, int op_code)
{
	int bit_offset;

	if (timer_index == 5) {
		switch (op_code) {
			case TIMER_OP_START:
				bit_offset = 24;
				break;

			case TIMER_OP_MANUAL:
				bit_offset = 25;
				break;

			case TIMER_OP_RELOAD:
				bit_offset = 26;
				break;

			default:
				return 0; /* invalid */
		}
	} else {
		bit_offset = op_code + (timer_index == 0 ? 0 : 8 + 4 * (timer_index - 1));
	}

	return (io.tcon & (0x1 << bit_offset));
}


static void s3c44b0x_timer_do_cycle(ARMul_State *state)
{
	int i;

	for (i = 0; i < 6; i++) {
		if (s3c44b0x_timer_check_state(i, TIMER_OP_START) == 0) continue;

		/* WARNING: PRESCALER & DIVIDER is unexacting */
		if (io.ttmp[i] > 31) {
			io.ttmp[i] -= 31;
			continue;
		} else {
			io.ttmp[i] = io.ttmpb[i];
		}

		if (io.tcnt[i] > 0) io.tcnt[i] -= 1;

#if 0
		if (io.tcnt[i] == io.tcmp[i]) {
			/* Turn TOUTn from low to high */
		}
#endif

		if (io.tcnt[i] > 0) continue;

		if ((io.tcfg1 & (i + 1)) == 0) { /* interrupt mode */
			s3c44b0x_set_interrupt(INT_TIMER0 - i);
		}

		if (s3c44b0x_timer_check_state(i, TIMER_OP_RELOAD) == 0) continue;

		io.tcnt[i] = io.tcntb[i];
		if (i < 5) io.tcmp[i] = io.tcmpb[i];

#if 0
		if (!(i == 5 || io.tcmp[i] < io.tcnt[i])) {
			/* Turn TOUTn to high */
		}
#endif
	}
}


static void s3c44b0x_timer_read(ARMword addr, ARMword *data)
{
	switch (addr) {
		case TCFG0:
			*data = io.tcfg0;
			break;

		case TCFG1:
			*data = io.tcfg1;
			break;

		case TCON:
			*data = io.tcon;
			break;

		case TCNTB0:
		case TCNTB1:
		case TCNTB2:
		case TCNTB3:
		case TCNTB4:
		case TCNTB5:
			*data = io.tcntb[(addr - TCNTB0) / 0xc];

		case TCMPB0:
		case TCMPB1:
		case TCMPB2:
		case TCMPB3:
		case TCMPB4:
			*data = io.tcmpb[(addr - TCMPB0) / 0xc];
			break;

		case TCNTO0:
		case TCNTO1:
		case TCNTO2:
		case TCNTO3:
		case TCNTO4:
			*data = io.tcnt[(addr - TCNTO0) / 0xc];
			break;

		case TCNTO5:
			*data = io.tcnt[5];
			break;

		default:
			break;
	}

//	DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data);
}


static void s3c44b0x_timer_write(ARMul_State *state, ARMword addr, ARMword data)
{
	int i, prescaler, divider;

//	DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data);

	switch (addr) {
		case TCFG0:
		case TCFG1:
			if (addr == TCFG0) {
				io.tcfg0 = data;
			} else {
				io.tcfg1 = data;
			}
			for (i = 0; i < 6; i++) {
				prescaler = (io.tcfg0 >> ((i >> 1) << 3)) & 0xff;
				divider = (io.tcfg1 >> (i << 2)) & 0xf;
				divider = (2 << (divider < 4 ? divider : 4));
				io.ttmp[i] = io.ttmpb[i] = (prescaler + 1) * (divider >> 1) - 1;
			}
			break;

		case TCON:
			io.tcon = data;
			for (i = 0; i < 6; i++) {
				if (s3c44b0x_timer_check_state(i, TIMER_OP_MANUAL) != 0) {
					io.tcnt[i] = io.tcntb[i];
					if (i < 5) io.tcmp[i] = io.tcmpb[i];
				}
#if 0
				if (i < 5 && s3c44b0x_timer_check_state(i, TIMER_OP_START) == 0) {
					if (io.tcnt[i] > io.tcmp[i]) {
						/* Turn TOUTn to low */
					} else {
						/* Turn TOUTn to high */
					}
				}
#endif
			}
			break;

		case TCNTB0:
		case TCNTB1:
		case TCNTB2:
		case TCNTB3:
		case TCNTB4:
		case TCNTB5:
			io.tcntb[(addr - TCNTB0) / 0xc] = data;
			break;

		case TCMPB0:
		case TCMPB1:
		case TCMPB2:
		case TCMPB3:
		case TCMPB4:
			io.tcmpb[(addr - TCMPB0) / 0xc] = data;
			break;

		default:
			break;
	}
}


/* I/O Ports Routine */
static void s3c44b0x_ports_read(ARMword addr, ARMword *data)
{
	/* TODO */
	DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data);
}


static void s3c44b0x_ports_write(ARMul_State *state, ARMword addr, ARMword data)
{
	/* TODO */
	DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data);
}


/* RTC Routine */
static void s3c44b0x_rtc_read(ARMword addr, ARMword *data)
{
	/* TODO */
	DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, *data);
}


static void s3c44b0x_rtc_write(ARMul_State *state, ARMword addr, ARMword data)
{
	/* TODO */
	DEBUG("%s(addr:0x%x, data:0x%x)\n", __FUNCTION__, addr, data);
}


/* IO Read Routine */
static ARMword s3c44b0x_io_read_word(ARMul_State *state, ARMword addr)
{
	ARMword data = -1;

	/* Interrupt */
	if (addr >= INTCON && addr <= F_ISPC) {
		s3c44b0x_interrupt_read(addr, &data);
		return data;
	}

	/* UART */
	if (addr >= ULCON0 && addr <= UBRDIV1) {
		s3c44b0x_uart_read(addr, &data);
		return data;
	}

	/* Timer */
	if (addr >= TCFG0 && addr <= TCNTO5) {
		s3c44b0x_timer_read(addr, &data);
		return data;
	}

	/* I/O Ports */
	if (addr >= PCONA && addr <= EXTINTPND) {
		s3c44b0x_ports_read(addr, &data);
		return data;
	}

	/* RTC */
	if (addr >= RTCCON && addr <= TICINT) {
		s3c44b0x_rtc_read(addr, &data);
		return data;
	}

	/* TODO */
	switch (addr) {
		case SYSCFG:
			data = 0x01; /* FIXME */
			break;

		case NCACHBE0:
			data = io.ncachbe0;
			break;

		case NCACHBE1:
			data = io.ncachbe1;
			break;

		case SBUSCON:
			data = io.sbuscon;
			break;

		default:
			PRINT("ERROR: %s(0x%08x)\n", __FUNCTION__, addr);
			break;
	}

	return data;
}


static ARMword s3c44b0x_io_read_byte(ARMul_State *state, ARMword addr)
{
	s3c44b0x_io_read_word(state, addr);
}


static ARMword s3c44b0x_io_read_halfword(ARMul_State *state, ARMword addr)
{
	s3c44b0x_io_read_word(state, addr);
}


/* IO Write Routine */
static void s3c44b0x_io_write_word(ARMul_State *state, ARMword addr, ARMword data)
{
	/* Interrupt */
	if (addr >= INTCON && addr <= F_ISPC) {
		s3c44b0x_interrupt_write(state, addr, data);
		return;
	}

	/* UART */
	if (addr >= ULCON0 && addr <= UBRDIV1) {
		s3c44b0x_uart_write(state, addr, data);
		return;
	}

	/* Timer */
	if (addr >= TCFG0 && addr <= TCNTO5) {
		s3c44b0x_timer_write(state, addr, data);
		return;
	}

	/* I/O Ports */
	if (addr >= PCONA && addr <= EXTINTPND) {
		s3c44b0x_ports_write(state, addr, data);
		return;
	}

	/* RTC */
	if (addr >= RTCCON && addr <= TICINT) {
		s3c44b0x_rtc_write(state, addr, data);
		return;
	}

	/* TODO */
	switch (addr) {
		case SYSCFG:
			io.syscfg = data;
			break;

		case NCACHBE0:
			io.ncachbe0 = data;
			break;

		case NCACHBE1:
			io.ncachbe1 = data;
			break;

		case SBUSCON:
			io.sbuscon = data;
			break;

		default:
			PRINT("ERROR: %s(0x%08x)\n", __FUNCTION__, addr);
			break;
	}
}


static void s3c44b0x_io_write_byte(ARMul_State *state, ARMword addr, ARMword data)
{
	s3c44b0x_io_write_word(state, addr, data);
}


static void s3c44b0x_io_write_halfword(ARMul_State * state, ARMword addr, ARMword data)
{
	s3c44b0x_io_write_word(state, addr, data);
}


static void s3c44b0x_io_do_cycle(ARMul_State *state)
{
	/* TODO */
	s3c44b0x_uart_do_cycle(state);
	s3c44b0x_timer_do_cycle(state);
	s3c44b0x_update_int(state);
}


/* Machine Initialization */
#define MACH_IO_DO_CYCLE_FUNC(f)	((void (*)(void*))(f))
#define MACH_IO_RESET_FUNC(f)		((void (*)(void*))(f))
#define MACH_IO_READ_FUNC(f)		((uint32_t (*)(void*, uint32_t))(f))
#define MACH_IO_WRITE_FUNC(f)		((void (*)(void *, uint32_t, uint32_t))(f))
#define MACH_IO_UPDATE_INT_FUNC(f)	((void (*)(void*))(f))
#define MACH_IO_SET_INTR_FUNC(f)	((void (*)(u32))(f))
#define MACH_IO_PENDING_INTR_FUNC(f)	((int (*)(u32))(f))
#define MACH_IO_UPDATE_INTR_FUNC(f)	((void (*)(void*))(f))

void s3c44b0x_mach_init(ARMul_State *state, machine_config_t *this_mach)
{
	ARMul_SelectProcessor(state, ARM_v4_Prop);
	state->lateabtSig = HIGH;

	state->Reg[1] = 178; /* R1: machine type : found in linux-2.6.x/include/asm/mach-types.h */

	this_mach->mach_io_do_cycle = MACH_IO_DO_CYCLE_FUNC(s3c44b0x_io_do_cycle);
	this_mach->mach_io_reset = MACH_IO_RESET_FUNC(s3c44b0x_io_reset);

	this_mach->mach_io_read_word = MACH_IO_READ_FUNC(s3c44b0x_io_read_word);
	this_mach->mach_io_read_halfword = MACH_IO_READ_FUNC(s3c44b0x_io_read_halfword);
	this_mach->mach_io_read_byte = MACH_IO_READ_FUNC(s3c44b0x_io_read_byte);
	this_mach->mach_io_write_word = MACH_IO_WRITE_FUNC(s3c44b0x_io_write_word);
	this_mach->mach_io_write_halfword = MACH_IO_WRITE_FUNC(s3c44b0x_io_write_halfword);
	this_mach->mach_io_write_byte = MACH_IO_WRITE_FUNC(s3c44b0x_io_write_byte);

	this_mach->mach_update_int = MACH_IO_UPDATE_INT_FUNC(s3c44b0x_update_int);
	this_mach->mach_set_intr = MACH_IO_SET_INTR_FUNC(s3c44b0x_set_interrupt);
	this_mach->mach_pending_intr = MACH_IO_PENDING_INTR_FUNC(s3c44b0x_pending_intr);
	this_mach->mach_update_intr = MACH_IO_UPDATE_INTR_FUNC(s3c44b0x_update_intr);

	this_mach->state = (void*)state; /* for LCD */
}