📄 board.h
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/* Defines used by the PCI auto configuraion code. */
/*---------------------------------------------------------------------*/
/* PCI Memory and IO spaces for plug & play - Viewed from processor. */
/* (all values are viewed from the CPU adress space.) */
/*---------------------------------------------------------------------*/
#define PCI_PP_MEM_START 0x80000000
#define PCI_PP_MEM_SIZE 0x04000000
#define PCI_PP_IO_START 0x88000000
#define PCI_PP_IO_SIZE 0x01000000
#define PCI2_PP_MEM_START 0x90000000
#define PCI2_PP_IO_START 0x98000000
#if 0
#define PCI_PP_IO16_START 0x90000000
#define PCI_PP_IO16_SIZE 0x91000000
#endif
/*---------------------------------------------------------------------*/
/* BRD_PCIMEM_CPU2PCI(addr, bridge) */
/* mapping the PCI memory address from CPU view to PCI view */
/* */
/* BRD_PCIIO_CPU2PCI(addr, bridge) */
/* mapping the PCI IO address from CPU view to PCI view */
/* */
/* BRD_PCIIO_PCI2CPU(addr, bridge) */
/* mapping the PCI IO address from PCI view to CPU view */
/* */
/* BRD_PCIMEM_PCI2CPU(addr, bridge) */
/* mapping the PCI memory address from PCI view to CPU view */
/*---------------------------------------------------------------------*/
/* Note: "bridge" reserved for the multi Host-PCI bridges support in */
/* the future. */
/*---------------------------------------------------------------------*/
#define BRD_PCIMEM_CPU2PCI(addr, bridge) (addr)
#define BRD_PCIIO_CPU2PCI(addr, bridge) (addr)
#define BRD_PCIMEM_PCI2CPU(addr, bridge) (addr)
#define BRD_PCIIO_PCI2CPU(addr, bridge) (addr)
/*---------------------------------------------------------------------*/
/* To pass a memory address (of the onboard memory) to PCI device for */
/* DMA data transfer, we have first to convert this address for PCI */
/* view. Since MPU and PCI addresses for system memory is same (from */
/* 0x00000000 to 0x3FFFFFFF), all we have to do is change the endianess*/
/*---------------------------------------------------------------------*/
/*---------------------------------------------------------------------*/
/* All devices are on the PCI bus which is little endian and PPC works */
/* in the big-endian. */
/*---------------------------------------------------------------------*/
#define BRD_CPU2DEV_LONG(x) ( \
(((unsigned long)(x) << 24) & 0xFF000000) | \
(((unsigned long)(x) << 8) & 0x00FF0000) | \
(((unsigned long)(x) >> 8) & 0x0000FF00) | \
(((unsigned long)(x) >> 24) & 0x000000FF) )
#define BRD_CPU2DEV_SHORT(x) ( (((unsigned short)(x) << 8) & 0xFF00) | \
(((unsigned short)(x) >> 8) & 0x00FF) )
/*---------------------------------------------------------------------*/
/* To pass a memory address (of the onboard memory) to PCI device for */
/* DMA data transfer, we have first to convert this address for PCI */
/* view. */
/*---------------------------------------------------------------------*/
#if 0
#define BRD_DEV2CPU_ADDR(x) (void *)((((ULONG)(x)&0xFF) == 0xFD) ? \
BRD_CPU2DEV_LONG(x) & 0x00ffffff : \
BRD_CPU2DEV_LONG(x))
#define BRD_CPU2DEV_ADDR(x) (void *)((ULONG)(x) & 0xFF000000 ? \
BRD_CPU2DEV_LONG(x) : \
(BRD_CPU2DEV_LONG(x) | 0xFD) )
#else
#define BRD_DEV2CPU_ADDR(x) BRD_CPU2DEV_LONG(x)
#define BRD_CPU2DEV_ADDR(x) BRD_CPU2DEV_LONG(x)
#endif
/*---------------------------------------------------------------------*/
/* Convert Little Endian to Big Endian and vice versa. */
/*---------------------------------------------------------------------*/
#define ULONG_LE2BE(x) BRD_CPU2DEV_LONG(x)
#define ULONG_BE2LE(x) BRD_CPU2DEV_LONG(x)
#define USHORT_BE2LE(x) BRD_CPU2DEV_SHORT(x)
#define USHORT_LE2BE(x) BRD_CPU2DEV_SHORT(x)
/*---------------------------------------------------------------------*/
/* Address and Data ports for PCI Configuration space. */
/*---------------------------------------------------------------------*/
#define PCI_CONFIG_ADDR PCI_CFG_ADR_REG
#define PCI_CONFIG_DATA PCI_CFG_DATA_REG
#define PCI2_CONFIG_ADDR PCI2_CFG_ADR_REG
#define PCI2_CONFIG_DATA PCI2_CFG_DATA_REG
/*---------------------------------------------------------------------*/
/* General definitions according to the PCI spec */
/*---------------------------------------------------------------------*/
#define MAXPCIDEV 32 /* Number of PCI devices on a bus */
/*---------------------------------------------------------------------*/
/* ISA IO Space Map - Viewed from the processor - Contiguous */
/*---------------------------------------------------------------------*/
#define BRD_ISA_LEG_IO_BASE ISA_IO_BASE /* Legacy IO Registers */
#define SL82565_REG_BASE ISA_IO_BASE /* ISA port registers */
/*---------------------------------------------------------------------*/
/* NVRAM addresses */
/*---------------------------------------------------------------------*/
#define NV_RTC_ADR0 REG8(0xFE000074) /* NVRAM ADDR LO PORT */
#define NV_RTC_ADR1 REG8(0xFE000075) /* NVRAM ADDR HI PORT */
#define NV_RTC_DATA REG8(0xFE000076) /* NVRAM DATA PORT */
#define NV_ETHER_OFFSET 0x1ef8 /* Ethernet address offset*/
#define ISASIO_KBD_REG REG8(0xFE000060) /* ISASIO: KeyBrd Ctrl */
#define ISASIO_PARALLEL 0xFE000278 /* ISASIO: Parallel Port */
#define ISASIO_FLOPPY0 REG32(0xFE0003F0) /* ISASIO: Reserved Floppy*/
#define ISASIO_FLOPPY1 REG32(0xFE0003F4) /* ISASIO: Reserved Floppy*/
#define ISASIO_COM1 0xFfe80008 /* ISASIO:Serl Port1(COM1)*/
#define ISASIO_COM2 0xFfe80000 /* ISASIO:Serl Port2(COM2)*/
/*---------------------------------------------------------------------*/
/* specify if use DMA for IDE drives. */
/*---------------------------------------------------------------------*/
#define BRD_IDE_USE_DMA YES
/*---------------------------------------------------------------------*/
/* This hash define controls which tick timer will be used as the */
/* pSOS+ timer. If it is defined as YES (default) the decrementer on */
/* the processor will be used, otherwise the 8254 compatible timer will*/
/* be the pSOS+ timer. */
/*---------------------------------------------------------------------*/
#define DEC_TICK_TIMER YES
/*---------------------------------------------------------------------*/
/* Overhead and rounding value that is used in the final */
/* calculation of the rtcDecTimeConst. */
/*---------------------------------------------------------------------*/
#define BD_RTC_ADJUST_COUNT 20
#define BD_VALIDATE_TICK2SEC (anchor->psosct->kc_ticks2sec == 0)
/*---------------------------------------------------------------------*/
/* specify if use DMA for IDE drives. */
/*---------------------------------------------------------------------*/
#define BRD_IDE_USE_DMA YES
/*---------------------------------------------------------------------*/
/* PCI Interrupt Acknowledge Register. Performing a read from this */
/* register will initiate a single PCI Interrupt Acknowledge Cycle. */
/* It will return the IRQ value from the Programable Interrupt */
/* Contorller (PIC). The PIC is contained in the */
/* PCI ISA Bridge (PIB) device. */
/*---------------------------------------------------------------------*/
#define BRD_PCI_IACK(x) x = REG8(0xFEF00000)
/*---------------------------------------------------------------------*/
/* Yellowknife Board Revisions */
/*---------------------------------------------------------------------*/
#define YK_X2 0
#define YK_X4 1
#define YK_SANDPNT 2
/*---------------------------------------------------------------------*/
/* 3COM ISA CARD IDS */
/*---------------------------------------------------------------------*/
#define ID_3COM509A 0x509A
#define ID_3COM509B 0x1998
#define BDCOM_V100 1
/*---------------------------------------------------------------------*/
/* leads to the outside world (some may not be supported) */
/*---------------------------------------------------------------------*/
#define LEAD_RXD 0
#define LEAD_TXD 1
#define LEAD_TCLK 2
#define LEAD_RCLK 3
#define LEAD_DTR 4
#define LEAD_DSR 5
#define LEAD_RTS 6
#define LEAD_CTS 7
#define LEAD_CD 8
#ifndef MAX_LEADS
#define MAX_LEADS 9
#endif
/*******************************************************************/
#define OFF_BOARD_INFO_ADDRESS 0x06c10000 /*flash sdram type,switch 32bit*/
#define FLASH_TYPE_OFF_BOARD (((*(ULONG*)OFF_BOARD_INFO_ADDRESS)&0x70000000)>>28)
#define SDRAM_TYPE_OFF_BOARD (((*(ULONG*)OFF_BOARD_INFO_ADDRESS)&0x07000000)>>24)
#define HW_PASS_SWITCH_DISABLE (((*(ULONG*)OFF_BOARD_INFO_ADDRESS)&0x80000000)>>31)
#define HW_RESV_SWITCH_DISABLE (((*(ULONG*)OFF_BOARD_INFO_ADDRESS)&0x08000000)>>27)
#define FLASH_TYPE_OFF_BOARD_NONE 0x7
#define FLASH_TYPE_OFF_BOARD_INTEL 0x3
#define FLASH_TYPE_OFF_BOARD_MACRONIX4M 0x4
#define FLASH_TYPE_OFF_BOARD_AMDATMEL4M 0x6
#define FLASH_TYPE_OFF_BOARD_AMDATMEL8M 0x5
/* Base address of DS1747 registers set */
#define RTC_BASE 0xE407FFF8
#define FLASH_TYPE_ON_BOARD_BASEADDR_IXP425 0x51000000
#define FLASH_TYPE_ON_BOARD_SIZE (8*MBYTE)
#define FLASH_LOGI_BASEADDR 0 /*FLASH_TYPE_ON_BOARD_BASEADDR*/
#define SDRAM_TYPE_OFF_BOARD_NONE 0x7
#define SDRAM_TYPE_OFF_BOARD_MICRON16M 0x5
#define SDRAM_TYPE_OFF_BOARD_MICRON32M 0x3
#define BD_EPROM_BASE_ADDR 0x50000000
#define BD_WATCHDOG_ADDR 0xFFE40001 /*by bspcfg.c*/
#define LOGIC_READ_ADDR 0xffe40002
#define LOGIC_WRITE_ADDR 0xffe40002
#define LED_3860_ACTIVE 0Xe4080000
/*---------------------------------------------------------------------*/
/* Definitions for bsps/devices/serial/pc16x50.c */
/*---------------------------------------------------------------------*/
#define BD_PC16X50_CLOCK_INPUT(channel) 14745600
#define BD_PC16X50_NCHANNELS 1
#define BD_PC16X50_UART_ADDRS 0xc8001000
#define BD_PC16X50_INT_NRS 13
/*---------------------------------------------------------------------*/
/* Definitions for bsps/devices/common/flash.c */
/*---------------------------------------------------------------------*/
#define FLASH_INFO_NUM 1 /* 1 onboard + 1 card */
#define FLASH_LONG(x) ( \
(((unsigned long)(x) << 24) & 0xFF000000) | \
(((unsigned long)(x) << 8) & 0x00FF0000) | \
(((unsigned long)(x) >> 8) & 0x0000FF00) | \
(((unsigned long)(x) >> 24) & 0x000000FF) )
#define FLASH_SHORT(x) ( (((unsigned short)(x) << 8) & 0xFF00) | \
(((unsigned short)(x) >> 8) & 0x00FF) )
#define FLASH_J3_DELAY 300
#define PCI_SUPPORT_NONE 0
#define PCI_SUPPORT_KERNL 1 /* Kernel PCI Support*/
#define PCI_SUPPORT_QSPAN 2 /* QSpan II */
#define PCI_SUPPORT_PSPAN 3 /* PowerSpan II */
#define PCI_SUPPORT_PQII 4 /* 8260 PQII */
#define ALIGN(addr, boundary) ((addr + boundary - 1) & ~(boundary - 1))
#define KBYTE 1024
#define MBYTE (KBYTE * KBYTE)
#define FLASH_TYPE_NONE 0
#define FLASH_TYPE_INTEL 1
#endif /* _BOARD_H */
#if __cplusplus
}
#endif
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