📄 board.h
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/***********************************************************************/
/* */
/* MODULE: bsps/5000/src/board.h */
/* DATE: 99/05/26 */
/* PURPOSE: Board specific information. This module should include */
/* all base device addresses and board specific macros. */
/* */
/***********************************************************************/
/*#include <icontrol/mpc.h>*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _BOARD_H
#define _BOARD_H
#include "global.h"
#define ISA_PRI_TO_IRQ(x) (((x) < 3) ? x : ((x) > 10 ? x - 8 : (x) + 5))
#define ISA_IRQ_TO_PRI(x) (((x) < 3) ? x : ((x) < 8 ? x + 8 : (x) - 5))
#define YES 1
#define NO 0
/*---------------------------------------------------------------------*/
/* Definitions for bsps/devices/parallel/sioparll.c */
/*---------------------------------------------------------------------*/
#define BD_SIO_PARALLEL_VALIDATE (void)TRUE /* parallel port present */
/*---------------------------------------------------------------------*/
/* External Function Declarations */
/* Cache Management Routines */
/*---------------------------------------------------------------------*/
/*---------------------------------------------------------------------*/
/* MMU Related Functions */
/*---------------------------------------------------------------------*/
extern void DsiExpHndlr(void);
extern void ItlbMissHndlr(void);
extern void DLStlbMissHndlr(void);
extern void ppcBATSclr(void);
extern void ppcBATset(ULONG type, ULONG num, ULONG Uval, ULONG Lval);
extern void ppcSEGset(ULONG segNum, ULONG Value);
extern ULONG ppcSEGget(ULONG segNum);
extern void ppcSEGSset(void);
extern void ppcTLBinv(ULONG num);
/*---------------------------------------------------------------------*/
/* Serial I/O Defines */
/*---------------------------------------------------------------------*/
#define BD_ALLOW_INTERRUPTS {}
#define BD_DISALLOW_INTERRUPTS {}
/*---------------------------------------------------------------------*/
/* Timer Defines */
/*---------------------------------------------------------------------*/
#define BD_SECOND_TIMER_VALUE 100
/*---------------------------------------------------------------------*/
/* Specify the BSP has the PCI plug-and-play support. */
/*---------------------------------------------------------------------*/
#define BRD_PCI_PLUG_AND_PLAY YES
#define BRD_PCI_SUB_BUS_SUPPORT YES
/*---------------------------------------------------------------------*/
/* Maximum chips supported by the 21X40 driver */
/*---------------------------------------------------------------------*/
#define BRD_MAX_D21X40_CHANNELS 2
/*---------------------------------------------------------------------*/
/* The following defines specify cache & snoop capabilities of the */
/* hardware and the mode of operation in pSOSystem, i.e. cache */
/* disabled, instruction cache enabled only and both instruction and */
/* data caches enabled. */
/* */
/* THE FOLLOWING THREE SETS OF DEFINES ARE REPEATED IN cpuarch.a. THEIR*/
/* CONSISTENCY MUST BE MAINTAINED BETWEEN THE TWO FILES. */
/* */
/* Specify the presence of Caches. */
/*---------------------------------------------------------------------*/
#define BRD_ICACHE YES /* Instruction Cache PRESENT */
#define BRD_DCACHE YES /* Data Cache PRESENT */
#define BRD_L2CACHE NO /* L2 Cache PRESENT */
/*---------------------------------------------------------------------*/
/* Data cache write policy selection. */
/* "YES" -- write-through policy. */
/* "NO" -- write-back policy. */
/*---------------------------------------------------------------------*/
#define BRD_DCACHE_WRITE_THRU YES
/*---------------------------------------------------------------------*/
/* Specify Data Cache organization. Some processors rigidly specify */
/* cache modes for the entire address space, while other such as the */
/* the PowerPC allow the mode to be modified at a page boundary. These */
/* defines are for processors that rigidly define cache mode. */
/*---------------------------------------------------------------------*/
#define BRD_DCACHE_WR_THRO 2 /* Data Cache is write through */
#define BRD_DCACHE_WR_BACK 3 /* Data Cache is write back */
/*---------------------------------------------------------------------*/
/* Specify Data Cache manipulation capabilities. */
/*---------------------------------------------------------------------*/
#define BRD_DCACHE_LINE_FLUSH YES /* Flushing a line is supported */
#define BRD_DCACHE_LINE_INV YES /* Invalidating a line is supported*/
/*---------------------------------------------------------------------*/
/* Specify Snoop capabilities of the processor & board. */
/* */
/* Notes: BRD_TX_SNOOP should be YES if the hardware has the capability*/
/* of providing the most recent data when a device reads from */
/* main memory and the the most recent copy is present in the */
/* data cache. */
/* */
/* BRD_TX_SNOOP should be YES if the data cache is organized as */
/* write through, wheter snooping is supported or not. Theis is */
/* because the most recent copy of data will always be provided */
/* when a device reads data from main memory. */
/* */
/* BRD_RX_SNOOP should be YES if the hardware has the capability*/
/* of updating the cache when a device writes to main memory. */
/* */
/* Some processors provide partial snooping capabilities. For */
/* example, the 68060 provides the capability of invalidating a */
/* data cache line when another bus master updates main memory */
/* but does not provide the bus with the most recent copy of */
/* data in the data cache when another bus master executes a */
/* read from main memory. Thus, for the 68060 BRD_RX_SNOOP */
/* would be YES and BRD_TX_SNOOP would be NO. If the data cache */
/* is set in write through mode BRD_TX_SNOOP should be set to */
/* YES. */
/* */
/*---------------------------------------------------------------------*/
#define BRD_TX_SNOOP YES /* Snoop support for Transmit */
#define BRD_RX_SNOOP YES /* Snoop support for Receive */
#if 0
/*---------------------------------------------------------------------*/
/* Perform Sanity Checks. */
/*---------------------------------------------------------------------*/
#if ((BRD_RX_SNOOP == NO) && (BRD_DCACHE == NO))
#error "Set Receive Snooping to YES if there is NO Data Cache"
#endif
#if ((BRD_TX_SNOOP == NO) && (BRD_DCACHE == NO))
#error "Set Transmit Snooping to YES if there is NO Data Cache"
#endif
#if ((BRD_TX_SNOOP == NO) && (BRD_DCACHE == BRD_DCACHE_WR_THRO))
#error "Set Transmit Snooping to YES for a Write Through Data Cache"
#endif
/*---------------------------------------------------------------------*/
/* Perform PowerPC specific sanity checks */
/*---------------------------------------------------------------------*/
#if ((BRD_DCACHE == YES) && (BSP_MMU == NO))
#error "Must enable the MMU for Data Cache Support"
#endif
#endif
/*---------------------------------------------------------------------*/
/* Check if the cache can be enabled. */
/*---------------------------------------------------------------------*/
/*#if (BRD_DCACHE == YES && (BRD_TX_SNOOP == NO || BRD_RX_SNOOP == NO))
#error "You had better turn the Data cache Off"
#else*/
#define BRD_TX_NOSNOOP(addr, len) {} /* Null Macro */
#define BRD_RX_NOSNOOP(addr, len) {} /* Null Macro */
/*#endif*/
#define ISA_INTERRUPT_BASE 0x0
#define EXT_INTERRUPT_BASE 0x10
#define TIMER_INTERRUPT_BASE 0x20
#define PIB_INT_VEC 0x00
/*---------------------------------------------------------------------*/
/* Interrupt Vector Levels */
/*---------------------------------------------------------------------*/
#define V_TICK 0x00 /* IBC Timer Counter 1 */
#define V_KBD 0x01 /* Keyboard */
#define V_SLAVE 0x02 /* SLAVE 8259 */
#define V_TIMER 0x03 /* 8254 Timer */
#define V_RSVD1 0x04 /* Reserved */
#define V_PERR 0x05 /* INTA PCI */
#define V_RSVD2 0x06 /* Reserved */
#define V_MOUSE 0x07 /* Mouse */
#define V_RSVD3 0x08 /* Reserved */
#define V_IDE 0x09 /* IDE Primary Port IRQ # 14 */
#define V_IDE2 0x0a /* IDE Secondary Port */
#define V_COM2 0x14 /* COM2 Serial Port */
#define V_COM1 0x14 /* COM1 Serial Port */
#define V_ISA1 0x0d /* ISA Slot 1 - network card */
#define V_FLPY 0x0e /* Floppy */
#define V_PARLL 0x0f /* Parallel Port */
#define V_INTA 0x05 /* INTA PCI */
#define V_INTB 0x06 /* INTB PCI */
#define V_INTC 0x09 /* INTC PCI */
#define V_INTD 0x0a /* INTD PCI */
/*---------------------------------------------------------------------*/
/* 8240 EPIC Interrupt Vector Levels */
/*---------------------------------------------------------------------*/
#define V_EPIC_LVL0 (0x00 + EXT_INTERRUPT_BASE)
#define V_EPIC_LVL1 (0x01 + EXT_INTERRUPT_BASE)
#define V_EPIC_LVL2 (0x02 + EXT_INTERRUPT_BASE)
#define V_EPIC_LVL3 (0x03 + EXT_INTERRUPT_BASE)
#define V_EPIC_SPURIOUS (0xFF)
/*---------------------------------------------------------------------*/
/* specify the mapping between Intr-Vector and ISA-IRQ */
/*---------------------------------------------------------------------*/
#define BRD_IVEC_TO_ISAPRI(ivec) (ivec - ISA_INTERRUPT_BASE)
#define BRD_ISAPRI_TO_IVEC(pri) (pri + ISA_INTERRUPT_BASE)
/*---------------------------------------------------------------------*/
/* Interrupt Level Mask Assignments */
/*---------------------------------------------------------------------*/
#define ISAINT2_IRQ08_TIMER 0x01 /* 8254 Timer */
#define ISAINT2_IRQ12_MOUSE 0x10 /* Mouse */
#define ISAINT2_IRQ13_RSVD 0x20 /* Reserved */
#define ISAINT2_IRQ14_IDE 0x40 /* IDE Primary Port */
#define ISAINT2_IRQ15_IDE2 0x80 /* IDE Secondary Port */
/*---------------------------------------------------------------------*/
/* Interrupt Level Bit Assignments */
/*---------------------------------------------------------------------*/
#define ISAINT1_BIT00_IBCTMR1 0x00 /* IBC Timer Counter 1 */
#define ISAINT1_BIT01_KBD 0x01 /* Keyboard */
#define ISAINT1_BIT03_COM2 0x03 /* COM2 Serial Port */
#define ISAINT1_BIT04_COM1 0x04 /* COM1 Serial Port */
#define ISAINT1_BIT05_ISA1 0x05 /* ISA Slot 1 */
#define ISAINT1_BIT06_FLPY 0x06 /* Floppy */
#define ISAINT1_BIT07_PARLL 0x07 /* Parallel Port */
#define ISAINT2_BIT00_TIMER 0x00 /* 8254 Timer */
#define ISAINT2_BIT04_MOUSE 0x04 /* Mouse */
#define ISAINT2_BIT05_RSVD 0x05 /* Reserved */
#define ISAINT2_BIT06_IDE 0x06 /* IDE Primary Port */
#define ISAINT2_BIT07_IDE2 0x06 /* IDE Secondary Port */
/*---------------------------------------------------------------------*/
/* Interrupt Level for PCI slots */
/*---------------------------------------------------------------------*/
#define BRD_CPCI_INTA_IRQ 10
#define BRD_CPCI_INTB_IRQ 11
#define BRD_CPCI_INTC_IRQ 14
#define BRD_CPCI_INTD_IRQ 15
/*---------------------------------------------------------------------*/
/* PCI IDE device IDs */
/*---------------------------------------------------------------------*/
#define BRD_PCI_IDE_IDS PIB_IDE_IDS
/*---------------------------------------------------------------------*/
/* Clock Rate definitions */
/*---------------------------------------------------------------------*/
#define CONFIG_SYS_CLK_FREQ 33333333
/*---------------------------------------------------------------------*/
/* Processor View of the Memory Map */
/*---------------------------------------------------------------------*/
#define DRAM_BASE 0x00000000 /* DRAM base address */
#define DRAM_END 0x3FFFFFFF /* Max. DRAM address */
#define DRAM_SPEED 100 /* 100 ns */
/*---------------------------------------------------------------------*/
/* Following subset of PCI IO is used by ISA IO space. */
/*---------------------------------------------------------------------*/
#define ISA_IO_BASE PCI_IO_BASE
/*---------------------------------------------------------------------*/
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