📄 immap_85xx.h
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u_char fccs;
char res5[3];
u_char ftirr_phy[4];
} ccsr_cpm_fcc2_t;
/* 0x91340-0x9137f: FCC3 */
typedef struct ccsr_cpm_fcc3 {
uint gfmr;
uint fpsmr;
ushort ftodr;
char res1[2];
ushort fdsr;
char res2[2];
ushort fcce;
char res3[2];
ushort fccm;
char res4[2];
u_char fccs;
char res5[3];
char res[36];
} ccsr_cpm_fcc3_t;
/* 0x91380-0x9139f: FCC1 extended */
typedef struct ccsr_cpm_fcc1_ext {
uint firper;
uint firer;
uint firsr_h;
uint firsr_l;
u_char gfemr;
char res[15];
} ccsr_cpm_fcc1_ext_t;
/* 0x913a0-0x913cf: FCC2 extended */
typedef struct ccsr_cpm_fcc2_ext {
uint firper;
uint firer;
uint firsr_h;
uint firsr_l;
u_char gfemr;
char res[31];
} ccsr_cpm_fcc2_ext_t;
/* 0x913d0-0x913ff: FCC3 extended */
typedef struct ccsr_cpm_fcc3_ext {
u_char gfemr;
char res[47];
} ccsr_cpm_fcc3_ext_t;
/* 0x91400-0x915ef: TC layers */
typedef struct ccsr_cpm_tmp1 {
char res[496];
} ccsr_cpm_tmp1_t;
/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
typedef struct ccsr_cpm_brg2 {
uint brgc5;
uint brgc6;
uint brgc7;
uint brgc8;
char res[608];
} ccsr_cpm_brg2_t;
/* 0x91860-0x919bf: I2C */
typedef struct ccsr_cpm_i2c {
u_char i2mod;
char res1[3];
u_char i2add;
char res2[3];
u_char i2brg;
char res3[3];
u_char i2com;
char res4[3];
u_char i2cer;
char res5[3];
u_char i2cmr;
char res6[331];
} ccsr_cpm_i2c_t;
/* 0x919c0-0x919ef: CPM core */
typedef struct ccsr_cpm_cp {
uint cpcr;
uint rccr;
char res1[14];
ushort rter;
char res2[2];
ushort rtmr;
ushort rtscr;
char res3[2];
uint rtsr;
char res4[12];
} ccsr_cpm_cp_t;
/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
typedef struct ccsr_cpm_brg1 {
uint brgc1;
uint brgc2;
uint brgc3;
uint brgc4;
} ccsr_cpm_brg1_t;
/* 0x91a00-0x91a9f: SCC1-SCC4 */
typedef struct ccsr_cpm_scc {
uint gsmrl;
uint gsmrh;
ushort psmr;
char res1[2];
ushort todr;
ushort dsr;
ushort scce;
char res2[2];
ushort sccm;
char res3;
u_char sccs;
char res4[8];
} ccsr_cpm_scc_t;
/* 0x91a80-0x91a9f */
typedef struct ccsr_cpm_tmp2 {
char res[32];
} ccsr_cpm_tmp2_t;
/* 0x91aa0-0x91aff: SPI */
typedef struct ccsr_cpm_spi {
ushort spmode;
char res1[4];
u_char spie;
char res2[3];
u_char spim;
char res3[2];
u_char spcom;
char res4[82];
} ccsr_cpm_spi_t;
/* 0x91b00-0x91b1f: CPM MUX */
typedef struct ccsr_cpm_mux {
u_char cmxsi1cr;
char res1;
u_char cmxsi2cr;
char res2;
uint cmxfcr;
uint cmxscr;
char res3[2];
ushort cmxuar;
char res4[16];
} ccsr_cpm_mux_t;
/* 0x91b20-0xbffff: SI,MCC,etc */
typedef struct ccsr_cpm_tmp3 {
char res[58592];
} ccsr_cpm_tmp3_t;
typedef struct ccsr_cpm_iram {
unsigned long iram[8192];
char res[98304];
} ccsr_cpm_iram_t;
typedef struct ccsr_cpm {
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
#define im_dprambase im_dpram1
u_char im_dpram1[16*1024];
char res1[16*1024];
u_char im_dpram2[16*1024];
char res2[16*1024];
ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
ccsr_cpm_fcc1_t im_cpm_fcc1;
ccsr_cpm_fcc2_t im_cpm_fcc2;
ccsr_cpm_fcc3_t im_cpm_fcc3;
ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
ccsr_cpm_tmp1_t im_cpm_tmp1;
ccsr_cpm_brg2_t im_cpm_brg2;
ccsr_cpm_i2c_t im_cpm_i2c;
ccsr_cpm_cp_t im_cpm_cp;
ccsr_cpm_brg1_t im_cpm_brg1;
ccsr_cpm_scc_t im_cpm_scc[4];
ccsr_cpm_tmp2_t im_cpm_tmp2;
ccsr_cpm_spi_t im_cpm_spi;
ccsr_cpm_mux_t im_cpm_mux;
ccsr_cpm_tmp3_t im_cpm_tmp3;
ccsr_cpm_iram_t im_cpm_iram;
} ccsr_cpm_t;
#endif
/* RapidIO Registers(0xc_0000-0xe_0000) */
typedef struct ccsr_rio {
uint didcar; /* 0xc0000 - Device Identity Capability Register */
uint dicar; /* 0xc0004 - Device Information Capability Register */
uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
uint aicar; /* 0xc000c - Assembly Information Capability Register */
uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
uint socar; /* 0xc0018 - Source Operations Capability Register */
uint docar; /* 0xc001c - Destination Operations Capability Register */
char res1[32];
uint msr; /* 0xc0040 - Mailbox Command And Status Register */
uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
char res2[4];
uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
char res3[12];
uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
char res4[4];
uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
char res5[144];
uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
char res6[28];
uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
char res7[20];
uint pgccsr; /* 0xc013c - Port General Command and Status Register */
uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
char res8[12];
uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
uint pccsr; /* 0xc015c - Port Control Command and Status Register */
char res9[65184];
uint cr; /* 0xd0000 - Port Control Command and Status Register */
char res10[12];
uint pcr; /* 0xd0010 - Port Configuration Register */
uint peir; /* 0xd0014 - Port Error Injection Register */
char res11[3048];
uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
char res12[12];
uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
char res13[12];
uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
char res14[4];
uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
char res15[4];
uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
char res16[12];
uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
char res17[4];
uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
char res18[4];
uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
char res19[12];
uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
char res20[4];
uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
char res21[4];
uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
char res22[12];
uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
char res23[4];
uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
char res24[4];
uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
char res25[12];
uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
char res26[4];
uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
char res27[4];
uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
char res28[12];
uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
char res29[4];
uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
char res30[4];
uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
char res31[12];
uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
char res32[4];
uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
char res33[4];
uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
char res34[12];
uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
char res35[4];
uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
char res36[4];
uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
char res37[76];
uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
char res38[4];
uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
char res39[4];
uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
char res40[12];
uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
char res41[4];
uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
char res42[4];
uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
char res43[12];
uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
char res44[4];
uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
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