immap_85xx.h

这是ARM在Vxworks的驱动源代码

	uint	eivpr10;	/* 0x50140 - External Interrupt Vector/Priority Register 10 */
	char	res67[12];
	uint	eidr10;		/* 0x50150 - External Interrupt Destination Register 10 */
	char	res68[12];
	uint	eivpr11;	/* 0x50160 - External Interrupt Vector/Priority Register 11 */
	char	res69[12];
	uint	eidr11;		/* 0x50170 - External Interrupt Destination Register 11 */
	char	res70[140];
	uint	iivpr0;		/* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
	char	res71[12];
	uint	iidr0;		/* 0x50210 - Internal Interrupt Destination Register 0 */
	char	res72[12];
	uint	iivpr1;		/* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
	char	res73[12];
	uint	iidr1;		/* 0x50230 - Internal Interrupt Destination Register 1 */
	char	res74[12];
	uint	iivpr2;		/* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
	char	res75[12];
	uint	iidr2;		/* 0x50250 - Internal Interrupt Destination Register 2 */
	char	res76[12];
	uint	iivpr3;		/* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
	char	res77[12];
	uint	iidr3;		/* 0x50270 - Internal Interrupt Destination Register 3 */
	char	res78[12];
	uint	iivpr4;		/* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
	char	res79[12];
	uint	iidr4;		/* 0x50290 - Internal Interrupt Destination Register 4 */
	char	res80[12];
	uint	iivpr5;		/* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
	char	res81[12];
	uint	iidr5;		/* 0x502b0 - Internal Interrupt Destination Register 5 */
	char	res82[12];
	uint	iivpr6;		/* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
	char	res83[12];
	uint	iidr6;		/* 0x502d0 - Internal Interrupt Destination Register 6 */
	char	res84[12];
	uint	iivpr7;		/* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
	char	res85[12];
	uint	iidr7;		/* 0x502f0 - Internal Interrupt Destination Register 7 */
	char	res86[12];
	uint	iivpr8;		/* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
	char	res87[12];
	uint	iidr8;		/* 0x50310 - Internal Interrupt Destination Register 8 */
	char	res88[12];
	uint	iivpr9;		/* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
	char	res89[12];
	uint	iidr9;		/* 0x50330 - Internal Interrupt Destination Register 9 */
	char	res90[12];
	uint	iivpr10;	/* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
	char	res91[12];
	uint	iidr10;		/* 0x50350 - Internal Interrupt Destination Register 10 */
	char	res92[12];
	uint	iivpr11;	/* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
	char	res93[12];
	uint	iidr11;		/* 0x50370 - Internal Interrupt Destination Register 11 */
	char	res94[12];
	uint	iivpr12;	/* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
	char	res95[12];
	uint	iidr12;		/* 0x50390 - Internal Interrupt Destination Register 12 */
	char	res96[12];
	uint	iivpr13;	/* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
	char	res97[12];
	uint	iidr13;		/* 0x503b0 - Internal Interrupt Destination Register 13 */
	char	res98[12];
	uint	iivpr14;	/* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
	char	res99[12];
	uint	iidr14;		/* 0x503d0 - Internal Interrupt Destination Register 14 */
	char	res100[12];
	uint	iivpr15;	/* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
	char	res101[12];
	uint	iidr15;		/* 0x503f0 - Internal Interrupt Destination Register 15 */
	char	res102[12];
	uint	iivpr16;	/* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
	char	res103[12];
	uint	iidr16;		/* 0x50410 - Internal Interrupt Destination Register 16 */
	char	res104[12];
	uint	iivpr17;	/* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
	char	res105[12];
	uint	iidr17;		/* 0x50430 - Internal Interrupt Destination Register 17 */
	char	res106[12];
	uint	iivpr18;	/* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
	char	res107[12];
	uint	iidr18;		/* 0x50450 - Internal Interrupt Destination Register 18 */
	char	res108[12];
	uint	iivpr19;	/* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
	char	res109[12];
	uint	iidr19;		/* 0x50470 - Internal Interrupt Destination Register 19 */
	char	res110[12];
	uint	iivpr20;	/* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
	char	res111[12];
	uint	iidr20;		/* 0x50490 - Internal Interrupt Destination Register 20 */
	char	res112[12];
	uint	iivpr21;	/* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
	char	res113[12];
	uint	iidr21;		/* 0x504b0 - Internal Interrupt Destination Register 21 */
	char	res114[12];
	uint	iivpr22;	/* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
	char	res115[12];
	uint	iidr22;		/* 0x504d0 - Internal Interrupt Destination Register 22 */
	char	res116[12];
	uint	iivpr23;	/* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
	char	res117[12];
	uint	iidr23;		/* 0x504f0 - Internal Interrupt Destination Register 23 */
	char	res118[12];
	uint	iivpr24;	/* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
	char	res119[12];
	uint	iidr24;		/* 0x50510 - Internal Interrupt Destination Register 24 */
	char	res120[12];
	uint	iivpr25;	/* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
	char	res121[12];
	uint	iidr25;		/* 0x50530 - Internal Interrupt Destination Register 25 */
	char	res122[12];
	uint	iivpr26;	/* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
	char	res123[12];
	uint	iidr26;		/* 0x50550 - Internal Interrupt Destination Register 26 */
	char	res124[12];
	uint	iivpr27;	/* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
	char	res125[12];
	uint	iidr27;		/* 0x50570 - Internal Interrupt Destination Register 27 */
	char	res126[12];
	uint	iivpr28;	/* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
	char	res127[12];
	uint	iidr28;		/* 0x50590 - Internal Interrupt Destination Register 28 */
	char	res128[12];
	uint	iivpr29;	/* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
	char	res129[12];
	uint	iidr29;		/* 0x505b0 - Internal Interrupt Destination Register 29 */
	char	res130[12];
	uint	iivpr30;	/* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
	char	res131[12];
	uint	iidr30;		/* 0x505d0 - Internal Interrupt Destination Register 30 */
	char	res132[12];
	uint	iivpr31;	/* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
	char	res133[12];
	uint	iidr31;		/* 0x505f0 - Internal Interrupt Destination Register 31 */
	char	res134[4108];
	uint	mivpr0;		/* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
	char	res135[12];
	uint	midr0;		/* 0x51610 - Messaging Interrupt Destination Register 0 */
	char	res136[12];
	uint	mivpr1;		/* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
	char	res137[12];
	uint	midr1;		/* 0x51630 - Messaging Interrupt Destination Register 1 */
	char	res138[12];
	uint	mivpr2;		/* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
	char	res139[12];
	uint	midr2;		/* 0x51650 - Messaging Interrupt Destination Register 2 */
	char	res140[12];
	uint	mivpr3;		/* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
	char	res141[12];
	uint	midr3;		/* 0x51670 - Messaging Interrupt Destination Register 3 */
	char	res142[59852];
	uint	ipi0dr0;	/* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
	char	res143[12];
	uint	ipi0dr1;	/* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
	char	res144[12];
	uint	ipi0dr2;	/* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
	char	res145[12];
	uint	ipi0dr3;	/* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
	char	res146[12];
	uint	ctpr0;		/* 0x60080 - Current Task Priority Register for Processor 0 */
	char	res147[12];
	uint	whoami0;	/* 0x60090 - Who Am I Register for Processor 0 */
	char	res148[12];
	uint	iack0;		/* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
	char	res149[12];
	uint	eoi0;		/* 0x600b0 - End Of Interrupt Register for Processor 0 */
	char	res150[130892];
} ccsr_pic_t;

/* CPM Block(0x8_0000-0xc_0000) */
#ifdef CONFIG_MPC8540
typedef struct ccsr_cpm {
	char res[262144];
} ccsr_cpm_t;
#else
/* 0x8000-0x8ffff:DPARM */

/* 0x9000-0x90bff: General SIU */
typedef struct ccsr_cpm_siu {
	char 	res1[80];
	uint	smaer;
	uint	smser;
	uint	smevr;
	char    res2[4];
	uint	lmaer;
	uint	lmser;
	uint	lmevr;
	char	res3[2964];
} ccsr_cpm_siu_t;

/* 0x90c00-0x90cff: Interrupt Controller */
typedef struct ccsr_cpm_intctl {
	ushort  sicr;
	char    res1[2];
	uint    sivec;
	uint    sipnrh;
	uint    sipnrl;
	uint    siprr;
	uint    scprrh;
	uint    scprrl;
	uint    simrh;
	uint    simrl;
	uint    siexr;
	char    res2[88];
	uint	sccr;
	char	res3[124];
} ccsr_cpm_intctl_t;

/* 0x90d00-0x90d7f: input/output port */
typedef struct ccsr_cpm_iop {
	uint    pdira;
	uint    ppara;
	uint    psora;
	uint    podra;
	uint    pdata;
	char    res1[12];
	uint    pdirb;
	uint    pparb;
	uint    psorb;
	uint    podrb;
	uint    pdatb;
	char    res2[12];
	uint    pdirc;
	uint    pparc;
	uint    psorc;
	uint    podrc;
	uint    pdatc;
	char    res3[12];
	uint    pdird;
	uint    ppard;
	uint    psord;
	uint    podrd;
	uint    pdatd;
	char    res4[12];
} ccsr_cpm_iop_t;

/* 0x90d80-0x91017: CPM timers */
typedef struct ccsr_cpm_timer {
	u_char  tgcr1;
	char    res1[3];
	u_char  tgcr2;
	char    res2[11];
	ushort  tmr1;
	ushort  tmr2;
	ushort  trr1;
	ushort  trr2;
	ushort  tcr1;
	ushort  tcr2;
	ushort  tcn1;
	ushort  tcn2;
	ushort  tmr3;
	ushort  tmr4;
	ushort  trr3;
	ushort  trr4;
	ushort  tcr3;
	ushort  tcr4;
	ushort  tcn3;
	ushort  tcn4;
	ushort  ter1;
	ushort  ter2;
	ushort  ter3;
	ushort  ter4;
	char    res3[608];
} ccsr_cpm_timer_t;

/* 0x91018-0x912ff: SDMA */
typedef struct ccsr_cpm_sdma {
	uchar	sdsr;
	char 	res1[3];
	uchar 	sdmr;
	char 	res2[739];
} ccsr_cpm_sdma_t;

/* 0x91300-0x9131f: FCC1 */
typedef struct ccsr_cpm_fcc1 {
	uint    gfmr;
	uint    fpsmr;
	ushort  ftodr;
	char    res1[2];
	ushort  fdsr;
	char    res2[2];
	ushort  fcce;
	char    res3[2];
	ushort  fccm;
	char    res4[2];
	u_char  fccs;
	char    res5[3];
	u_char  ftirr_phy[4];
} ccsr_cpm_fcc1_t;

/* 0x91320-0x9133f: FCC2 */
typedef struct ccsr_cpm_fcc2 {
	uint    gfmr;
	uint    fpsmr;
	ushort  ftodr;
	char    res1[2];
	ushort  fdsr;
	char    res2[2];
	ushort  fcce;
	char    res3[2];
	ushort  fccm;
	char    res4[2];