immap_85xx.h

这是ARM在Vxworks的驱动源代码

/*
 * MPC85xx Internal Memory Map
 *
 * Copyright(c) 2002,2003 Motorola Inc.
 * Xianghua Xiao ([e-mail])
 *
 */

#ifndef __IMMAP_85xx__
#define __IMMAP_85xx__


/* Local-Access Registers and ECM Registers(0x0000-0x2000) */

typedef struct ccsr_local_ecm {
	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
	char	res1[4];
	uint	altcbar;	/* 0x8 - Alternate Configuration Base Address Register */
	char	res2[4];
	uint	altcar;		/* 0x10 - Alternate Configuration Attribute Register */
	char	res3[12];
	uint	bptr;		/* 0x20 - Boot Page Translation Register */
	char	res4[3044];
	uint	lawbar0;	/* 0xc08 - Local Access Window 0 Base Address Register */
	char	res5[4];
	uint	lawar0;		/* 0xc10 - Local Access Window 0 Attributes Register */
	char	res6[20];
	uint	lawbar1;	/* 0xc28 - Local Access Window 1 Base Address Register */
	char	res7[4];
	uint	lawar1;		/* 0xc30 - Local Access Window 1 Attributes Register */
	char	res8[20];
	uint	lawbar2;	/* 0xc48 - Local Access Window 2 Base Address Register */
	char	res9[4];
	uint	lawar2;		/* 0xc50 - Local Access Window 2 Attributes Register */
	char	res10[20];
	uint	lawbar3;	/* 0xc68 - Local Access Window 3 Base Address Register */
	char	res11[4];
	uint	lawar3;		/* 0xc70 - Local Access Window 3 Attributes Register */
	char	res12[20];
	uint	lawbar4;	/* 0xc88 - Local Access Window 4 Base Address Register */
	char	res13[4];
	uint	lawar4;		/* 0xc90 - Local Access Window 4 Attributes Register */
	char	res14[20];
	uint	lawbar5;	/* 0xca8 - Local Access Window 5 Base Address Register */
	char	res15[4];
	uint	lawar5;		/* 0xcb0 - Local Access Window 5 Attributes Register */
	char	res16[20];
	uint	lawbar6;	/* 0xcc8 - Local Access Window 6 Base Address Register */
	char	res17[4];
	uint	lawar6;		/* 0xcd0 - Local Access Window 6 Attributes Register */
	char	res18[20];
	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
	char	res19[4];
	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
	char	res20[780];
	uint	eebacr;		/* 0x1000 - ECM CCB Address Configuration Register */
	char	res21[12];
	uint	eebpcr;		/* 0x1010 - ECM CCB Port Configuration Register */
	char	res22[3564];
	uint	eedr;		/* 0x1e00 - ECM Error Detect Register */
	char	res23[4];
	uint	eeer;		/* 0x1e08 - ECM Error Enable Register */
	uint	eeatr;		/* 0x1e0c - ECM Error Attributes Capture Register */
	uint	eeadr;		/* 0x1e10 - ECM Error Address Capture Register */
	char	res24[492];
} ccsr_local_ecm_t;


/* DDR memory controller registers(0x2000-0x3000) */

typedef struct ccsr_ddr {
	uint	cs0_bnds;		/* 0x2000 - DDR Chip Select 0 Memory Bounds */
	char	res1[4];
	uint	cs1_bnds;		/* 0x2008 - DDR Chip Select 1 Memory Bounds */
	char	res2[4];
	uint	cs2_bnds;		/* 0x2010 - DDR Chip Select 2 Memory Bounds */
	char	res3[4];
	uint	cs3_bnds;		/* 0x2018 - DDR Chip Select 3 Memory Bounds */
	char	res4[100];
	uint	cs0_config;		/* 0x2080 - DDR Chip Select Configuration */
	uint	cs1_config;		/* 0x2084 - DDR Chip Select Configuration */
	uint	cs2_config;		/* 0x2088 - DDR Chip Select Configuration */
	uint	cs3_config;		/* 0x208c - DDR Chip Select Configuration */
	char	res5[120];
	uint	timing_cfg_1;		/* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
	uint	timing_cfg_2;		/* 0x210c - DDR SDRAM Timing Configuration Register 2 */
	uint	sdram_cfg;		/* 0x2110 - DDR SDRAM Control Configuration */
	char	res6[4];
	uint	sdram_mode;		/* 0x2118 - DDR SDRAM Mode Configuration */
	char	res7[8];
	uint	sdram_interval;		/* 0x2124 - DDR SDRAM Interval Configuration */
	char	res8[3288];
	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
	char	res9[20];
	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
	uint	capture_ecc;		/* 0x2e28 - DDR Memory Data Path Read Capture ECC */
	char	res10[20];
	uint	err_detect;		/* 0x2e40 - DDR Memory Error Detect */
	uint	err_disable;		/* 0x2e44 - DDR Memory Error Disable */
	uint	err_int_en;		/* 0x2e48 - DDR  */
	uint	capture_attributes;	/* 0x2e4c - DDR Memory Error Attributes Capture */
	uint	capture_address;	/* 0x2e50 - DDR Memory Error Address Capture */
	uint	capture_ext_address;	/* 0x2e54 - DDR Memory Error Extended Address Capture */
	uint	err_sbe;		/* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
	char	res11[164];
	uint	debug_1;		/* 0x2f00 */
	uint	debug_2;
	uint	debug_3;
	uint	debug_4;
	char	res12[240];
} ccsr_ddr_t;


/* I2C Registers(0x3000-0x4000) */

typedef struct ccsr_i2c {
	u_char	i2cadr;		/* 0x3000 - I2C Address Register */
#define MPC85xx_I2CADR_MASK	0xFE
	char	res1[3];
	u_char	i2cfdr;		/* 0x3004 - I2C Frequency Divider Register */
#define MPC85xx_I2CFDR_MASK	0x3F
	char	res2[3];
	u_char	i2ccr;		/* 0x3008 - I2C Control Register */
#define MPC85xx_I2CCR_MEN	0x80
#define MPC85xx_I2CCR_MIEN	0x40
#define MPC85xx_I2CCR_MSTA      0x20
#define MPC85xx_I2CCR_MTX       0x10
#define MPC85xx_I2CCR_TXAK      0x08
#define MPC85xx_I2CCR_RSTA      0x04
#define MPC85xx_I2CCR_BCST      0x01
	char	res3[3];
	u_char	i2csr;		/* 0x300c - I2C Status Register */
#define MPC85xx_I2CSR_MCF	0x80
#define MPC85xx_I2CSR_MAAS      0x40
#define MPC85xx_I2CSR_MBB       0x20
#define MPC85xx_I2CSR_MAL       0x10
#define MPC85xx_I2CSR_BCSTM     0x08
#define MPC85xx_I2CSR_SRW       0x04
#define MPC85xx_I2CSR_MIF       0x02
#define MPC85xx_I2CSR_RXAK      0x01
	char	res4[3];
	u_char	i2cdr;		/* 0x3010 - I2C Data Register */
#define MPC85xx_I2CDR_DATA	0xFF
	char	res5[3];
	u_char	i2cdfsrr;	/* 0x3014 - I2C Digital Filtering Sampling Rate Register */
#define MPC85xx_I2CDFSRR	0x3F
	char	res6[4075];
} ccsr_i2c_t;

#ifdef CONFIG_MPC8540
/* DUART Registers(0x4000-0x5000) */
typedef struct ccsr_duart {
	char	res1[1280];
	u_char	urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
	u_char	uier1_udmb1;	/* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
	u_char	uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
	u_char	ulcr1;		/* 0x4503 - UART1 Line Control Register */
	u_char	umcr1;		/* 0x4504 - UART1 Modem Control Register */
	u_char	ulsr1;		/* 0x4505 - UART1 Line Status Register */
	u_char	umsr1;		/* 0x4506 - UART1 Modem Status Register */
	u_char	uscr1;		/* 0x4507 - UART1 Scratch Register */
	char	res2[8];
	u_char	udsr1;		/* 0x4510 - UART1 DMA Status Register */
	char	res3[239];
	u_char	urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
	u_char	uier2_udmb2;	/* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
	u_char	uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
	u_char	ulcr2;		/* 0x4603 - UART2 Line Control Register */
	u_char	umcr2;		/* 0x4604 - UART2 Modem Control Register */
	u_char	ulsr2;		/* 0x4605 - UART2 Line Status Register */
	u_char	umsr2;		/* 0x4606 - UART2 Modem Status Register */
	u_char	uscr2;		/* 0x4607 - UART2 Scratch Register */
	char	res4[8];
	u_char	udsr2;		/* 0x4610 - UART2 DMA Status Register */
	char	res5[2543];
} ccsr_duart_t;
#else /* MPC8560 uses UART on its CPM */
typedef struct ccsr_duart {
	char res[4096];
} ccsr_duart_t;
#endif

/* Local Bus Controller Registers(0x5000-0x6000) */
/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */

typedef struct ccsr_lbc {
	uint	br0;		/* 0x5000 - LBC Base Register 0 */
	uint	or0;		/* 0x5004 - LBC Options Register 0 */
	uint	br1;		/* 0x5008 - LBC Base Register 1 */
	uint	or1;		/* 0x500c - LBC Options Register 1 */
	uint	br2;		/* 0x5010 - LBC Base Register 2 */
	uint	or2;		/* 0x5014 - LBC Options Register 2 */
	uint	br3;		/* 0x5018 - LBC Base Register 3 */
	uint	or3;		/* 0x501c - LBC Options Register 3 */
	uint	br4;		/* 0x5020 - LBC Base Register 4 */
	uint	or4;		/* 0x5024 - LBC Options Register 4 */
	uint	br5;		/* 0x5028 - LBC Base Register 5 */
	uint	or5;		/* 0x502c - LBC Options Register 5 */
	uint	br6;		/* 0x5030 - LBC Base Register 6 */
	uint	or6;		/* 0x5034 - LBC Options Register 6 */
	uint	br7;		/* 0x5038 - LBC Base Register 7 */
	uint	or7;		/* 0x503c - LBC Options Register 7 */
	char	res1[40];
	uint	mar;		/* 0x5068 - LBC UPM Address Register */
	char	res2[4];
	uint	mamr;		/* 0x5070 - LBC UPMA Mode Register */
	uint	mbmr;		/* 0x5074 - LBC UPMB Mode Register */
	uint	mcmr;		/* 0x5078 - LBC UPMC Mode Register */
	char	res3[8];
	uint	mrtpr;		/* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
	uint	mdr;		/* 0x5088 - LBC UPM Data Register */
	char	res4[8];
	uint	lsdmr;		/* 0x5094 - LBC SDRAM Mode Register */
	char	res5[8];
	uint	lurt;		/* 0x50a0 - LBC UPM Refresh Timer */
	uint	lsrt;		/* 0x50a4 - LBC SDRAM Refresh Timer */
	char	res6[8];
	uint	ltesr;		/* 0x50b0 - LBC Transfer Error Status Register */
	uint	ltedr;		/* 0x50b4 - LBC Transfer Error Disable Register */
	uint	lteir;		/* 0x50b8 - LBC Transfer Error Interrupt Register */
	uint	lteatr;		/* 0x50bc - LBC Transfer Error Attributes Register */
	uint	ltear;		/* 0x50c0 - LBC Transfer Error Address Register */
	char	res7[12];
	uint	lbcr;		/* 0x50d0 - LBC Configuration Register */
	uint	lcrr;		/* 0x50d4 - LBC Clock Ratio Register */
	char	res8[12072];
} ccsr_lbc_t;


/* PCI Registers(0x8000-0x9000) */
/* Omitting Reserved(0x9000-0x2_0000) */

typedef struct ccsr_pcix {
	uint	cfg_addr;	/* 0x8000 - PCIX Configuration Address Register */
	uint	cfg_data;	/* 0x8004 - PCIX Configuration Data Register */
	uint	int_ack;	/* 0x8008 - PCIX Interrupt Acknowledge Register */
	char	res1[3060];
	uint	potar0;		/* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
	uint	potear0;	/* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
	uint	powbar0;	/* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
	uint	powbear0;	/* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
	uint	powar0;		/* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
	char	res2[12];
	uint	potar1;		/* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
	uint	potear1;	/* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
	uint	powbar1;	/* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
	uint	powbear1;	/* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
	uint	powar1;		/* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
	char	res3[12];
	uint	potar2;		/* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
	uint	potear2;	/* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
	uint	powbar2;	/* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
	uint	powbear2;	/* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
	uint	powar2;		/* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
	char	res4[12];
	uint	potar3;		/* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
	uint	potear3;	/* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
	uint	powbar3;	/* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
	uint	powbear3;	/* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
	uint	powar3;		/* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
	char	res5[12];
	uint	potar4;		/* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
	uint	potear4;	/* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
	uint	powbar4;	/* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
	uint	powbear4;	/* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
	uint	powar4;		/* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
	char	res6[268];
	uint	pitar3;		/* 0x8da0 - PCIX Inbound Translation Address Register 3  */
	uint	pitear3;	/* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
	uint	piwbar3;	/* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
	uint	piwbear3;	/* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
	uint	piwar3;		/* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
	char	res7[12];
	uint	pitar2;		/* 0x8dc0 - PCIX Inbound Translation Address Register 2  */
	uint	pitear2;	/* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
	uint	piwbar2;	/* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
	uint	piwbear2;	/* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
	uint	piwar2;		/* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
	char	res8[12];
	uint	pitar1;		/* 0x8de0 - PCIX Inbound Translation Address Register 1  */
	uint	pitear1;	/* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
	uint	piwbar1;	/* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
	char	res9[4];
	uint	piwar1;		/* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
	char	res10[12];
	uint	pedr;		/* 0x8e00 - PCIX Error Detect Register */
	uint	pecdr;		/* 0x8e04 - PCIX Error Capture Disable Register */
	uint	peer;		/* 0x8e08 - PCIX Error Enable Register */
	uint	peattrcr;	/* 0x8e0c - PCIX Error Attributes Capture Register */
	uint	peaddrcr;	/* 0x8e10 - PCIX Error Address Capture Register */
	uint	peextaddrcr;	/* 0x8e14 - PCIX  Error Extended Address Capture Register */
	uint	pedlcr;		/* 0x8e18 - PCIX Error Data Low Capture Register */
	uint	pedhcr;		/* 0x8e1c - PCIX Error Error Data High Capture Register */
	char	res11[480];

	uint	pci2_cfg_addr;	/* 0x8000 - PCIX Configuration Address Register */
	uint	pci2_cfg_data;	/* 0x8004 - PCIX Configuration Data Register */
	uint	pci2_int_ack;	/* 0x8008 - PCIX Interrupt Acknowledge Register */
	char	pci2_res1[3060];
	uint	pci2_potar0;		/* 0x8c00 - PCIX Outbound Transaction Address Register 0 */