📄 hal_regs.h
字号:
//===========================================================================
// HAL_REGS.H
// (Tabs set to every 4)
//---------------------------------------------------------------------------
// Copyright (c) 2002, 2003 Epson Research and Development, Inc.
// All Rights Reserved.
//===========================================================================
#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__
#define HAL_REGBYTES 2 // Size, in bytes, of register accesses for this chip.
#define HAL_REGSIZE 200 // Estimated maximum number of registers in HAL_STRUCT.
#define HAL_LCDSIZE 256 // Estimated maximum number of LCD entries in HAL_STRUCT.
#define HAL_REGCAMSIZE 200 // Estimated maximum number of initialization camera data.
// LCD Register Names
#define REG_LCD_BASE 0x0000
#define REG0000_PRODINFO 0x0000
#define REG0002_CFGPINS 0x0002
#define REG0006_BUSTIMEOUT 0x0006 // 13715 only
#define REG000E_PLL0 0x000E
#define REG0010_PLL1 0x0010
#define REG0012_PLL2 0x0012
#define REG0014_PWRSAVE 0x0014
#define REG0016_SOFTRESET 0x0016
#define REG0018_SYSCLK 0x0018
#define REG0020_IREADBACK 0x0020
#define REG0022_IMEMADDR1 0x0022
#define REG0024_IMEMADDR2 0x0024
#define REG0026_IAUTOINC 0x0026
#define REG0028_IMEMPORT 0x0028
#define REG002A_I2DRDWRPORT 0x002A
#define REG0030_LCDINTCLOCK 0x0030
#define REG0032_LCDMODCLOCK 0x0032
#define REG0034_LCDINTCMD 0x0034
#define REG0036_LCDINTPARAM 0x0036
#define REG0038_LCDINTSTATUS 0x0038
#define REG003A_LCDINTFRAMEXFER 0x003A
#define REG003C_LCDINTXFER 0x003C
#define REG0040_LCD1HT 0x0040
#define REG0042_LCD1HDP 0x0042
#define REG0044_LCD1HDPS 0x0044
#define REG0046_LCD1FPLINE 0x0046
#define REG0048_LCD1FPLINE2 0x0048
#define REG004A_LCD1VT 0x004A
#define REG004C_LCD1VDP 0x004C
#define REG004E_LCD1VDPS 0x004E
#define REG0050_LCD1FPFRAME 0x0050
#define REG0052_LCD1FPFRAME2 0x0052
#define REG0054_LCD1SER 0x0054
#define REG0056_LCD1PAR 0x0056
#define REG0058_LCD2HDP 0x0058
#define REG005A_LCD2VDP 0x005A
#define REG005C_LCD2SER 0x005C
#define REG005E_LCD2PAR 0x005E
#define REG0070_TFT5HT 0x0070 // 13715 only
#define REG0080_ATFTHT 0x0080
#define REG0082_ATFTLDRISING 0x0082
#define REG0084_ATFTCKVTOGGLE 0x0084
#define REG0086_ATFTVCOMTOGGLE 0x0086
#define REG0088_ATFTPULSE 0x0088
#define REG008A_TYPEHAP10 0x008A
#define REG008C_TYPEHAP11 0x008C
#define REG008E_TYPEHAP12 0x008E
#define REG0090_HRTFTCONFIG 0x0090
#define REG0092_HRTFTCLSWIDTH 0x0092
#define REG0094_HRTFTPS1RISING 0x0094
#define REG0096_HRTFTPS2RISING 0x0096
#define REG0098_HRTFTPS2TOGGLE 0x0098
#define REG009A_HRTFTPS3SIGNAL 0x009A
#define REG009E_HRTFTREVTOGGLE 0x009E
#define REG00A0_HRTFTPS12END 0x00A0
#define REG00A2_TYPE2TFTCONFIG 0x00A2
#define REG00A4_CASIOTIMING0 0x00A4
#define REG00A6_CASIOTIMING1 0x00A6
#define REG00A8_T3TFTCONFIG0 0x00A8
#define REG00AA_T3TFTCONFIG1 0x00AA // 13714 only
#define REG00AC_T3TFTCONFIG2 0x00AC // 13714 only
#define REG00AE_T3TFTCONFIG3 0x00AE // 13714 only
#define REG00B0_T3TFTPCLKDIV 0x00B0 // 13714 only
#define REG00B2_T3TFTPMODECTRL 0x00B2 // 13714 only
#define REG00B4_T3TFTPAREA0POS0 0x00B4 // 13714 only
#define REG00B6_T3TFTPAREA0POS1 0x00B6 // 13714 only
#define REG00B8_T3TFTPAREA1POS0 0x00B8 // 13714 only
#define REG00BA_T3TFTPAREA1POS1 0x00BA // 13714 only
#define REG00BC_T3TFTPAREA2POS0 0x00BC // 13714 only
#define REG00BE_T3TFTPAREA2POS1 0x00BE // 13714 only
#define REG00C0_T3TFTCMDSTORE0 0x00C0 // 13714 only
#define REG00C2_T3TFTCMDSTORE1 0x00C2 // 13714 only
#define REG00C4_TYPE3TFTMISC 0x00C4 // 13714 only
#define REG00C6_TYPEHDYSTREG0 0x00C6
#define REG00C8_TYPEHYSTREG1 0x00C8
#define REG00CA_TYPEHCOM 0x00CA
#define REG00CC_TYPEHDVNDP 0x00CC
#define REG00CE_TYPEHYCK 0x00CE
#define REG00D0_TYPEHDHT 0x00D0
#define REG00D2_TYPEHOE 0x00D2
#define REG00D4_TYPEHSTH 0x00D4
#define REG00D6_TYPEHLOAD 0x00D6
#define REG00D8_TYPEHASW0 0x00D8
#define REG00DA_TYPEHASW1 0x00DA
#define REG00DC_TYPEHASW2 0x00DC
#define REG00DE_TYPEHDHNDP 0x00DE
#define REG00E0_TYPEDMISC0 0x00E0
#define REG00E2_TYPEDMISC1 0x00E2
#define REG00E4_TYPEDMISC2 0x00E4
#define REG00E6_TYPEDMISC3 0x00E6
#define REG00E8_TYPEDMISC4 0x00E8
#define REG00EA_TOSHMISC 0x00EA
#define REG00EC_TYPEDSRAMMODE 0x00EC
#define REG00EE_PDRVA0START 0x00EE
#define REG00F0_PDRVA0END 0x00F0
#define REG00F2_PDRVA1START 0x00F2
#define REG00F4_PDRVA1END 0x00F4
#define REG00F6_PDRVA0SADDR0 0x00F6
#define REG00F8_PDRVA0SADDR1 0x00F8
#define REG00FA_PDRVA1SADDR0 0x00FA
#define REG00FC_PDRVA1SADDR1 0x00FC
#define REG00FE_LCDID 0x00FE // 13715 only
#define REG0100_CM1CLK 0x0100
#define REG0102_CM1SIGNAL 0x0102
#define REG0104_CM2CLKDIV 0x0104
#define REG0106_CM2INPUT 0x0106
#define REG0108_CM1TYPE2VCOUNT 0x0108
#define REG010A_CM1TYPE2HCOUNT 0x010A
#define REG010C_CM1TYPE2CTRL 0x010C
#define REG010E_CM1TYPE2STATUS 0x010E
#define REG0110_CAMERAMODE 0x0110
#define REG0112_CAMERAFRAME 0x0112
#define REG0114_CAMERACTRL 0x0114
#define REG0116_CAMERASTATUS 0x0116 // 13715 only
#define REG0120_STROBEDELAY 0x0120 // 13715 only
#define REG0122_STROBEWIDTH 0x0122 // 13715 only
#define REG0124_STROBECONTROL 0x0124 // 13715 only
#define REG0128_MPEGH 0x0128
#define REG012A_MPEGW 0x012A
#define REG0200_DISPMODE0 0x0200
#define REG0202_DISPMODE1 0x0202
#define REG0204_OVERLAYRED 0x0204
#define REG0206_OVERLAYGREEN 0x0206
#define REG0208_OVERLAYBLUE 0x0208
#define REG0210_DISPSTART0 0x0210
#define REG0212_DISPSTART1 0x0212
#define REG0214_START 0x0214
#define REG0216_LINEOFFSET 0x0216
#define REG0218_PIPDISPSTART0 0x0218
#define REG021A_PIPDISPSTART1 0x021A
#define REG021C_PIPSTART 0x021C
#define REG021E_PIPLINEOFFSET 0x021E
#define REG0220_PIPXSTART 0x0220
#define REG0222_PIPYSTART 0x0222
#define REG0224_PIPXEND 0x0224
#define REG0226_PIPYEND 0x0226
#define REG0228_PIPSTARTFIELD 0x0228
#define REG022A_BBSADDR0 0x022A // 13715 only
#define REG022C_BBSADDR1 0x022C // 13715 only
#define REG0240_YUVRGBXLATE 0x0240
#define REG0242_YUVWRSTART0R0 0x0242
#define REG0244_YUVWRSTART0R1 0x0244
#define REG0246_YUVWRSTART1R0 0x0246
#define REG0248_YUVWRSTART1R1 0x0248
#define REG024A_UVDATAFIX 0x024A
#define REG024C_YRCRPWIDTH 0x024C
#define REG024E_YRCRSTRIDE 0x024E
#define REG0260_RYCCONFIG 0x0260
#define REG0262_RYCUV 0x0262
#define REG0264_ENCODEHDP 0x0264
#define REG0266_ENCODEVDP 0x0266
#define REG0268_FIFOTHRESHOLD 0x0268
#define REG0270_MJPEGCONTROL 0x0270 // 13715 only
#define REG0272_MJPEGHORZPIXEL 0x0272 // 13715 only
#define REG0274_MJPEGVERTLINE 0x0274 // 13715 only
#define REG0276_MJPEGRGB0 0x0276 // 13715 only
#define REG0278_MJPEGRGB1 0x0278 // 13715 only
#define REG0280_NTSCDOUBL 0x0280
#define REG0300_GPIOSTATUS0 0x0300
#define REG0302_GPIOSTATUS1 0x0302
#define REG0304_GPIOSTATUS2 0x0304
#define REG0306_GPIOSTATUS3 0x0306
#define REG0308_GPIOPULLDOWN0 0x0308
#define REG030A_GPIOPULLDOWN1 0x030A
#define REG030C_GPIOSTATUS4 0x030C
#define REG030E_GPIOSTATUS5 0x030E
#define REG0310_AVGOVERLAYRED 0x0310
#define REG0312_AVGOVERLAYGREEN 0x0312
#define REG0314_AVGOVERLAYBLUE 0x0314
#define REG0316_ANDOVERLAYRED 0x0316
#define REG0318_ANDOVERLAYGREEN 0x0318
#define REG031A_ANDOVERLAYBLUE 0x031A
#define REG031C_OROVERLAYRED 0x031C
#define REG031E_OROVERLAYGREEN 0x031E
#define REG0320_OROVERLAYBLUE 0x0320
#define REG0322_INVOVERLAYRED 0x0322
#define REG0324_INVOVERLAYGREEN 0x0324
#define REG0326_INVOVERLAYBLUE 0x0326
#define REG0328_OVERLAYMISC 0x0328
#define REG0400_LUT1REG0 0x0400
#define REG0402_LUT1REG1 0x0402
#define REG0800_LUT2REG0 0x0800
#define REG0802_LUT2REG1 0x0802
#define REG0930_GLOBALRESIZE 0x0930
#define REG0932_ACTIVESEQ 0x0932
#define REG0938_RINTSET 0x0938
#define REG093A_RINTFLAG 0x093A
#define REG093C_RINTRESET 0x093C
#define REG093E_RINTENABLE 0x093E
#define REG0940_VIEWRESIZE 0x0940
#define REG0944_VRESIZESTARTX 0x0944
#define REG0946_VRESIZESTARTY 0x0946
#define REG0948_VRESIZEENDX 0x0948
#define REG094A_VRESIZEENDY 0x094A
#define REG094C_VRESIZEOP0 0x094C
#define REG094E_VRESIZEOP1 0x094E
#define REG0960_CRESIZECTRL 0x0960
#define REG0964_CRESIZESTARTX 0x0964
#define REG0966_CRESIZESTARTY 0x0966
#define REG0968_CRESIZEENDX 0x0968
#define REG096A_CRESIZEENDY 0x096A
#define REG096C_CRESIZEOP0 0x096C // 13714 only
#define REG096E_CRESIZEOP1 0x096E
#define REG0980_JPEGCTRL 0x0980
#define REG0982_JPEGSTATUS 0x0982
#define REG0984_JPEGRAWSTATUS 0x0984
#define REG0986_JPEGINT 0x0986
#define REG0988_JPEGRESET 0x0988
#define REG098A_JPEGSTARTSTOP 0x098A
#define REG098C_JPEGFRAMEC 0x098C
#define REG098E_JPEGPSIZEADJUST 0x098E
#define REG09A0_JPEGFIFOCTRL 0x09A0
#define REG09A2_JPEGFIFOSTATUS 0x09A2
#define REG09A4_JPEGFIFOSIZE 0x09A4
#define REG09A6_JPEGFIFORDWR 0x09A6
#define REG09A8_JPEGFIFOVDATA 0x09A8
#define REG09AA_JPEGFIFOREAD 0x09AA
#define REG09AC_JPEGFIFOWRITE 0x09AC
#define REG09B0_ENCODELIMIT0 0x09B0
#define REG09B2_ENCODELIMIT1 0x09B2
#define REG09B4_ENCODERESULT0 0x09B4
#define REG09B6_ENCODERESULT1 0x09B6
#define REG09B8_JPEGFILESIZE0 0x09B8
#define REG09BA_JPEGFILESIZE1 0x09BA
#define REG09BC_JPEGFIFOADDR 0x09BC
#define REG09C0_JPEGLINESTATUS 0x09C0
#define REG09C2_JPEGLINERAW 0x09C2
#define REG09C4_JPEGLINERAWC 0x09C4
#define REG09C6_JPEGLINEINT 0x09C6
#define REG09C8_JPEGIOBUF 0x09C8 // 13715 only
#define REG09CA_JPEGBANKLINES 0x09CA // 13715 only
#define REG09CC_JPEGBANKREMAINS 0x09CC // 13715 only
#define REG09CE_JPEGREADWRITE 0x09CE // 13715 only
#define REG09D0_JPEGLINECFG 0x09D0
#define REG09D2_JPEGLINEOFFSET 0x09D2
#define REG09D4_JPEGLINEBANKNUM 0x09D4
#define REG09D6_JPEGLINELPB 0x09D6
#define REG09D8_JPEGLINERRBN 0x09D8
#define REG09DA_JPEGLINEWBP 0x09DA
#define REG09DC_JPEGLINERBP 0x09DC
#define REG09DE_JPEGLINEREQMEM 0x09DE // 13715 only
#define REG09E0_JPEGLINEWRITE 0x09E0
#define REG0A00_INTSTATUS 0x0A00
#define REG0A02_INTCTRL0 0x0A02
#define REG0A04_INTCTRL1 0x0A04
#define REG0A06_DEBUGSTATUS 0x0A06
#define REG0A08_INTCTRLDEBUG 0x0A08
#define REG0A0A_HOSTINTSTATUS 0x0A0A
#define REG0A0C_HOSTINTCONTROL 0x0A0C
#define REG0A0E_CYCLETIMEOUT 0x0A0E
#define REG0A10_DEBUG 0x0A10
#define REG0A40_INTREQSTATUS 0x0A40 // 13715 only
#define REG0F00_JPEGPERF 0x0F00 // 13715 only
#define REG1000_OPMODE 0x1000
#define REG1002_COMMAND 0x1002
#define REG1004_JPEGOP 0x1004
#define REG1006_QUANTNUM 0x1006
#define REG1008_HUFFMANNUM 0x1008
#define REG100A_DRI0 0x100A
#define REG100C_DRI1 0x100C
#define REG100E_VERTPIXELSIZE0 0x100E
#define REG1010_VERTPIXELSIZE1 0x1010
#define REG1012_HORZPIXELSIZE0 0x1012
#define REG1014_HORZPIXELSIZE1 0x1014
#define REG1016_DNLVALUE0 0x1016
#define REG1018_DNLVALUE1 0x1018
#define REG101C_RSTOPSETTING 0x101C
#define REG101E_RSTOPSTATUS 0x101E
#define REG1020_JINSMARKER 0x1020
#define REG1200_JQUANT0 0x1200
#define REG1280_JQUANT1 0x1280
#define REG1400_JDCHUFF0REG0 0x1400
#define REG1420_JDCHUFF0REG1 0x1420
#define REG1440_JACHUFF0REG0 0x1440
#define REG1460_JACHUFF0REG1 0x1460
#define REG1600_JDCHUFF1REG0 0x1600
#define REG1620_JDCHUFF1REG1 0x1620
#define REG1640_JACHUFF1REG0 0x1640
#define REG1660_JACHUFF1REG1 0x1660
// BitBLT Register Names
#define REG_BLT_BASE 0x8000
#define REG8000_BLTCTRL0 0x8000
#define REG8002_BLTCTRL1 0x8002
#define REG8004_BLTSTATUS0 0x8004
#define REG8006_BLTSTATUS1 0x8006
#define REG8008_BLTCOMMAND0 0x8008
#define REG800A_BLTCOMMAND1 0x800A
#define REG800C_BLTSRCSTART0 0x800C
#define REG800E_BLTSRCSTART1 0x800E
#define REG8010_BLTDSTSTART0 0x8010
#define REG8012_BLTDSTSTART1 0x8012
#define REG8014_BLTMEMOFFSET 0x8014
#define REG8018_BLTW 0x8018
#define REG801C_BLTH 0x801C
#define REG8020_BLTBG 0x8020
#define REG8024_BLTFG 0x8024
#define REG8030_BLTINTSTATUS 0x8030
#define REG8032_BLTINTCTRL 0x8032
#define REG10000_BLTDATA 0x10000
#define REGFLAG_BASE 0xFFF0 // Special reserved flags above this point.
#define REGFLAG_PREPARECLKS 0xFFFA // Prepares Clocks Registers to Known State
#define REGFLAG_CONFIGURECLKS 0xFFFB // Configures Clock Registers
#define REGFLAG_PLLDELAY 0xFFFC // Indicates a microsecond delay for programming the PLL.
#define REGFLAG_OFFDELAY 0xFFFD // Indicates a millisecond delay for powering down LCD.
#define REGFLAG_ONDELAY 0xFFFE // Indicates a millisecond delay for powering up LCD.
#define REGFLAG_ENDOFTABLE 0xFFFF // End of register table flag.
#endif // __HAL_REGS_H__
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -