📄 sfcon.src
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MOV.L #addr_fdata,ER0 ; Source buffer
MOV.L @_flash_rw+6,ER1 ; Target buffer
;**** wait busy signal and perform data read
JSR @DMA_read ; including wait loop & read 512 bytes only
;**** ECC information read
MOV.L @_flash_rw+10,ER1 ; Target buffer
JSR @DMA_ecc ; always read 16 bytes only
SUB.W #512,R2 ; check length
BEQ fread_end
;**** prepare 2nd sector to read
MOV.L #addr_fdata,ER0 ; Source buffer
MOV.L @_flash_rw+6,ER1 ; Target buffer
ADD.L #512,ER1
;**** wait busy signal and perform data read
JSR @DMA_read ; including wait loop & read 512 bytes only
;**** ECC information read
MOV.L @_flash_rw+10,ER1 ; Target buffer
ADD.L #16,ER1
JSR @DMA_ecc ; always read 16 bytes only
SUB.W #512,R2 ; check length
BEQ fread_end
;**** prepare 3nd sector to read
MOV.L #addr_fdata,ER0 ; Source buffer
MOV.L @_flash_rw+6,ER1 ; Target buffer
ADD.L #1024,ER1
;**** wait busy signal and perform data read
JSR @DMA_read ; including wait loop & read 512 bytes only
;**** ECC information read
MOV.L @_flash_rw+10,ER1 ; Target buffer
ADD.L #32,ER1
JSR @DMA_ecc ; always read 16 bytes only
SUB.W #512,R2 ; check length
BEQ fread_end
;**** prepare 4nd sector to read
MOV.L #addr_fdata,ER0 ; Source buffer
MOV.L @_flash_rw+6,ER1 ; Target buffer
ADD.L #1536,ER1
;**** wait busy signal and perform data read
JSR @DMA_read ; including wait loop & read 512 bytes only
;**** ECC information read
MOV.L @_flash_rw+10,ER1 ; Target buffer
ADD.L #48,ER1
JSR @DMA_ecc ; always read 16 bytes only
fread_end:
POP.W R2
RTS
;****************************************************
;** WRITE data with length and page location
;****************************************************
;** - R0 location
;****************************************************
_fwrite_data:
PUSH.L ER2 ; push register ER2
fwrite_data_wait0:
BLD #f_io_busy,@porte
BCC fwrite_data_wait0
;*** write command
MOV.L #addr_fcmd,ER1 ; cmd address
MOV.B #cle_h,R2H
MOV.B R2H,@portbdr
MOV.B #fcmd_read10,R2L
CMP.W #255,R0
BLS write_cmd_loc
MOV.B #fcmd_read11,R2L
SUB.W #256,R0
CMP.W #255,R0
BLS write_cmd_loc
MOV.B #fcmd_read2,R2L
SUB.W #256,R0
write_cmd_loc:
MOV.B R2L,@ER1 ; write page location
MOV.B #fcmd_wr1,R2L
MOV.B R2L,@ER1 ; write h'80 write cmd
MOV.B #ale_h,R2H
MOV.B R2H,@portbdr
MOV.B R0L,@ER1 ; write location
MOV.W @_flash_rw+2,R0
MOV.B R0L,@ER1 ; write page address
MOV.B R0H,@ER1 ; write page address
MOV.B #ale_l,R0H
MOV.B R0H,@portbdr
;**** perpare Read data from Flash memory to buffer
MOV.W @_flash_rw+4,E2 ; Number of byte
MOV.L #addr_fdata,ER0 ; Target buffer
MOV.L @_flash_rw+6,ER1 ; Source buffer
;**** wait busy signal
fwrite_wait1:
BLD #f_io_busy,@porte
BCC fwrite_wait1
;**** perform data read
fwrite_wait2:
MOV.B @ER1+,R2L
MOV.B R2L,@ER0
DEC.W #1,E2
BNE fwrite_wait2
MOV.L #addr_fcmd,ER1 ; cmd address
MOV.B #cle_h,R0H
MOV.B R0H,@portbdr
MOV.B #fcmd_wr2,R0L
MOV.B R0L,@ER1 ; write H'10 (preform write cmd)
fwrite_data_complete:
BLD #f_io_busy,@porte
BCC fwrite_data_complete
MOV.L #addr_fcmd,ER1 ; cmd address
MOV.B #fcmd_read_status,R0L
MOV.B R0L,@ER1 ; write H'70 read status cmd
MOV.B #cle_l,R0H
MOV.B R0H,@portbdr
MOV.L #addr_fdata,ER1 ; store status
MOV.B @ER1,R0L
AND.B #H'01,R0L ; Mask out unwanted bit, non-zero error
POP.L ER2
RTS
;********************************************************
;** WRITE SECTOR
;********************************************************
;** - write information stored in struct "_flash_rw"
;** - cannot more than 2048 bytes
;** - length must in module of 512
;** - including ECC generation
;********************************************************
;** - write_sector (512 + 16 = 528 bytes OR by length)
;** - flash_rw stored information to read
;********************************************************
_fwrite_sector:
fwrite_sector_wait0:
BLD #f_io_busy,@porte
BCC fwrite_sector_wait0
;*** write 0~511 + 16 byte ECC
;JSR @_asm_genEccS:32 ; gen ECC
JSR @fwrite_page ; perform 1st 512 byte write
MOV.W @_flash_rw+4,R0
SUB.W #512,R0 ; check anymore to write
BEQ fwrite_wait_complete
;*** write 512~1023 + 16 byte ECC
MOV.W R0,@_flash_rw+4
MOV.W @_flash_rw+6,R0
ADD.W #512,R0
MOV.W R0,@_flash_rw+6
;JSR @_asm_genEccS:32 ; gen ECC
JSR @fwrite_page ; perform 2st 512 byte write
MOV.W @_flash_rw+4,R0
SUB.W #512,R0 ; check anymore to write
BEQ fwrite_wait_complete
;*** write 1024~1535 + 16 byte ECC
MOV.W R0,@_flash_rw+4
MOV.W @_flash_rw+6,R0
ADD.W #512,R0
MOV.W R0,@_flash_rw+6
;JSR @_asm_genEccS:32 ; gen ECC
JSR @fwrite_page ; perform 3st 512 byte write
MOV.W @_flash_rw+4,R0
SUB.W #512,R0 ; check anymore to write
BEQ fwrite_wait_complete
;*** write 1535~2047 + 16 byte ECC
MOV.W R0,@_flash_rw+4
MOV.W @_flash_rw+6,R0
ADD.W #512,R0
MOV.W R0,@_flash_rw+6
;JSR @_asm_genEccS:32 ; gen ECC
JSR @fwrite_page ; perform 4st 512 byte write
MOV.W @_flash_rw+4,R0
fwrite_wait_complete:
MOV.B @porte,R0L
BPL fwrite_wait_complete
MOV.L #addr_fcmd,ER1 ; cmd address
MOV.B #fcmd_read_status,R0L
MOV.B R0L,@ER1 ; write H'70 read status cmd
MOV.B #cle_l,R0H
MOV.B R0H,@portbdr
MOV.L #addr_fdata,ER1 ; store status
MOV.B @ER1,R0L
AND.B #H'01,R0L ; Mask out unwanted bit, non-zero error
RTS
;---- write page
fwrite_page:
;*** write command
MOV.L #addr_fcmd,ER1 ; cmd address
MOV.B #cle_h,R0H
MOV.B R0H,@portbdr
MOV.B #0,R0L
MOV.B R0L,@ER1 ; write H'00 (read cmd) to reset pointer
MOV.B #fcmd_wr1,R0L
MOV.B R0L,@ER1 ; write H'80 (write cmd) to flash memory
MOV.B #ale_h,R0H
MOV.B R0H,@portbdr
MOV.B #0,R0L ; always '0' for column addr
MOV.B R0L,@ER1
MOV.W @_flash_rw+2:16,R0 ; lower address
MOV.B R0L,@ER1
MOV.B R0H,@ER1
MOV.B #ale_l,R0H
MOV.B R0H,@portbdr
;**** perpare WRITE data to Flash memory
MOV.L @_flash_rw+6,ER0 ; Source buffer
MOV.L #addr_fdata,ER1 ; Target buffer
;**** wait busy signal and perform data read
JSR @DMA_write ; always write 512 bytes data only
;**** ECC information read
MOV.L @_flash_rw+10,ER0 ; Source buffer
;no write ECC at this moment
;JSR @DMA_ecc ; always write 16 bytes ecc code only
MOV.L #addr_fcmd,ER1 ; cmd address
MOV.B #cle_h,R0H
MOV.B R0H,@portbdr
MOV.B #fcmd_wr2,R0L
MOV.B R0L,@ER1 ; write H'10 (preform write cmd)
RTS
;********************************************************
;** COPY BACK SECTOR
;********************************************************
;** - copy a sector (page) from one location to another
;** - 1 page = 528 bytes
;********************************************************
;** - ER0 source address
;** - ER1 destination address
;********************************************************
_fcopy_back:
PUSH.L ER2
PUSH.L ER3
;*** write command
MOV.L #addr_fcmd,ER3 ; cmd address
MOV.B #cle_h,R2H
MOV.B R2H,@portbdr
MOV.B #fcmd_cpback1,R2L
MOV.B R2L,@ER3 ; write H'00 (read cmd) to reset pointer
MOV.B #ale_h,R2H
MOV.B R2H,@portbdr
MOV.B #0,R2L ; always '0' for column addr
MOV.B R2L,@ER3
MOV.B R0L,@ER3 ; src. page adderss (A9~A16)
MOV.B R0H,@ER3 ; src. page address (A17~A24)
MOV.B #ale_l,R2H
MOV.B R2H,@portbdr
MOV.B #cle_h,R2H ; prepare cmd to send after busy
MOV.B #fcmd_cpback2,R2L
MOV.B #ale_h,R0H
MOV.B #0,R0L
fcopy_wait:
BLD #f_io_busy,@porte ; wait read busy
BCC fcopy_wait
MOV.B R2H,@portbdr
MOV.B R2L,@ER3 ; write H'8A (copy back cmd) to reset pointer
MOV.B R0H,@portbdr
MOV.B R0L,@ER3 ; always '0' for column addr
MOV.B R1L,@ER3 ; dest. page adderss (A9~A16)
MOV.B R1H,@ER3 ; dest. page address (A17~A24)
MOV.B #ale_l,R2H
MOV.B R2H,@portbdr
MOV.B #fcmd_read_status,R0L ; prepare cmd to send after busy
MOV.L ER3,ER1 ; ER1 = cmd address
POP.L ER3
POP.L ER2
fcopy_complete:
MOV.B @porte,R0H ; wait write busy
BPL fcopy_complete
MOV.B R0L,@ER1 ; write H'70 read status cmd
MOV.B #cle_l,R0H
MOV.B R0H,@portbdr
MOV.B @ER1,R0L ; get status
AND.B #H'01,R0L ; Mask out unwanted bit, non-zero error
RTS
;*********************************************************************
;** DMAC1 for data transfer between Internal RAM <-> Flash Memory
;*********************************************************************
;** - transfer 512 bytes data using DMA for data
;** - transfer 16 bytes data using DMA for ECC code
;*********************************************************************
;** - ER0 source address
;** - ER1 destination address
;*********************************************************************
;
;**** For Flash Memroy <--> Internal RAM
DMA_write:
MOV.L ER0,@H'FFFEF0:16 ; wirte (Internal RAM) source addr. to MAR1A
MOV.L ER1,@H'FFFEF8:16 ; write (Flash Memory) destination addr. to MAR1B
MOV.W #H'2007:16,R0 ; transfer direction from Internal RAM -> Flash Memory
BRA DMA_access
DMA_read:
MOV.L ER0,@H'FFFEF0:16 ; wirte (Flash memory) source addr. to MAR1A
MOV.L ER1,@H'FFFEF8:16 ; write (Internal RAM) destination addr. to MAR1B
MOV.W #H'0027:16,R0 ; transfer direction from Flash Memory -> Internal RAM
DMA_access:
MOV.W R0,@H'FFFF64:16 ; DMAC1, Flash->RAM, byte access, src fixed, normal mode, dst+1, burst mode
MOV.W #H'40:16,E0 ; no. of byte to transfer
MOV.B #H'8,R1L ; transfer (512) 8 x 64 bytes
DMA_busy_wait:
MOV.B @porte,R0H ; wait flash access busy
BPL DMA_busy_wait
MOV.B #CS1_BUS,R0H
MOV.B R0H,@pgddr:16 ; CS1 control by bus
BSET #7,@H'FFFF67 ; DTME1=1, enable DMAC ch1
DMA_loop:
MOV.W E0,@H'FFFEF6:16 ; ETCR1A = 0x40
BSET #6,@H'FFFF67 ; DTE1=1, start DMAC ch1
DMA_loop1:
BLD #6,@H'FFFF67 ; check transfer finished
BCS DMA_loop1 ; finish if DTE1=0
DEC.B R1L
BNE DMA_loop ;
BCLR #7,@H'FFFF67 ; DTME1=0, disable DMAC ch1
RTS
;-- both read/write ecc can use same routine
DMA_ecc:
MOV.L ER1,@H'FFFEF8:16 ; write destination addr. to MAR1B
DMA_ecc_activate:
BSET #7,@H'FFFF67 ; DTME1=1, enable DMAC ch1
MOV.W #H'10:16,R0 ; no. of byte to transfer, 16 bytes ECC
MOV.W R0,@H'FFFEF6:16 ; ETCR1A = 0x10
BSET #6,@H'FFFF67 ; DTE1=1, start DMAC ch1
DMA_ecc_wait:
BLD #6,@H'FFFF67 ; check transfer finished
BCS DMA_ecc_wait
BCLR #7,@H'FFFF67 ; DTME1=0, disable DMAC chl
RTS
.END
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