untitled.laf

上载硬部线学校课程设计

   PIN Z0 OUT T__79;
   PIN A0 IN GATE_T__79_N_1;
   PIN A1 IN GATE_T__79_N_2;
 END;
 SYM INV GATE_T__80_I_2;
   PIN ZN0 OUT GATE_T__80_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__80_I_1;
   PIN ZN0 OUT GATE_T__80_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__80_U1;
   PIN Z0 OUT T__80;
   PIN A0 IN GATE_T__80_N_1;
   PIN A1 IN GATE_T__80_N_2;
 END;
 SYM INV GATE_T__81_I_1;
   PIN ZN0 OUT GATE_T__81_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__81_U1;
   PIN Z0 OUT T__81;
   PIN A0 IN GATE_T__81_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__82_I_1;
   PIN ZN0 OUT GATE_T__82_N_1;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM AND2 GATE_T__82_U1;
   PIN Z0 OUT T__82;
   PIN A0 IN GATE_T__82_N_1;
   PIN A1 IN IN_IR4_U1_Z0;
 END;
 SYM INV GATE_T__83_I_2;
   PIN ZN0 OUT GATE_T__83_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__83_I_1;
   PIN ZN0 OUT GATE_T__83_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__83_U1;
   PIN Z0 OUT T__83;
   PIN A0 IN GATE_T__83_N_1;
   PIN A1 IN GATE_T__83_N_2;
 END;
 SYM INV GATE_T__84_I_2;
   PIN ZN0 OUT GATE_T__84_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__84_I_1;
   PIN ZN0 OUT GATE_T__84_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__84_U1;
   PIN Z0 OUT T__84;
   PIN A0 IN GATE_T__84_N_1;
   PIN A1 IN GATE_T__84_N_2;
 END;
 SYM INV GATE_T__85_I_1;
   PIN ZN0 OUT GATE_T__85_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__85_U1;
   PIN Z0 OUT T__85;
   PIN A0 IN GATE_T__85_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__86_I_2;
   PIN ZN0 OUT GATE_T__86_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__86_I_1;
   PIN ZN0 OUT GATE_T__86_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__86_U1;
   PIN Z0 OUT T__86;
   PIN A0 IN GATE_T__86_N_1;
   PIN A1 IN GATE_T__86_N_2;
 END;
 SYM INV GATE_T__87_I_2;
   PIN ZN0 OUT GATE_T__87_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__87_I_1;
   PIN ZN0 OUT GATE_T__87_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__87_U1;
   PIN Z0 OUT T__87;
   PIN A0 IN GATE_T__87_N_1;
   PIN A1 IN GATE_T__87_N_2;
 END;
 SYM INV GATE_T__88_I_1;
   PIN ZN0 OUT GATE_T__88_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__88_U1;
   PIN Z0 OUT T__88;
   PIN A0 IN GATE_T__88_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__89_I_2;
   PIN ZN0 OUT GATE_T__89_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__89_I_1;
   PIN ZN0 OUT GATE_T__89_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__89_U1;
   PIN Z0 OUT T__89;
   PIN A0 IN GATE_T__89_N_1;
   PIN A1 IN GATE_T__89_N_2;
 END;
 SYM INV GATE_T__90_I_2;
   PIN ZN0 OUT GATE_T__90_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__90_I_1;
   PIN ZN0 OUT GATE_T__90_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__90_U1;
   PIN Z0 OUT T__90;
   PIN A0 IN GATE_T__90_N_1;
   PIN A1 IN GATE_T__90_N_2;
 END;
 SYM INV GATE_T__91_I_1;
   PIN ZN0 OUT GATE_T__91_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__91_U1;
   PIN Z0 OUT T__91;
   PIN A0 IN GATE_T__91_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__92_I_2;
   PIN ZN0 OUT GATE_T__92_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__92_I_1;
   PIN ZN0 OUT GATE_T__92_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__92_U1;
   PIN Z0 OUT T__92;
   PIN A0 IN GATE_T__92_N_1;
   PIN A1 IN GATE_T__92_N_2;
 END;
 SYM INV GATE_T__93_I_2;
   PIN ZN0 OUT GATE_T__93_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__93_I_1;
   PIN ZN0 OUT GATE_T__93_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__93_U1;
   PIN Z0 OUT T__93;
   PIN A0 IN GATE_T__93_N_1;
   PIN A1 IN GATE_T__93_N_2;
 END;
 SYM INV GATE_T__94_I_1;
   PIN ZN0 OUT GATE_T__94_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__94_U1;
   PIN Z0 OUT T__94;
   PIN A0 IN GATE_T__94_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__95_I_1;
   PIN ZN0 OUT GATE_T__95_N_1;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM AND2 GATE_T__95_U1;
   PIN Z0 OUT T__95;
   PIN A0 IN GATE_T__95_N_1;
   PIN A1 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__96_I_2;
   PIN ZN0 OUT GATE_T__96_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__96_I_1;
   PIN ZN0 OUT GATE_T__96_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__96_U1;
   PIN Z0 OUT T__96;
   PIN A0 IN GATE_T__96_N_1;
   PIN A1 IN GATE_T__96_N_2;
 END;
 SYM INV GATE_T__97_I_2;
   PIN ZN0 OUT GATE_T__97_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__97_I_1;
   PIN ZN0 OUT GATE_T__97_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__97_U1;
   PIN Z0 OUT T__97;
   PIN A0 IN GATE_T__97_N_1;
   PIN A1 IN GATE_T__97_N_2;
 END;
 SYM INV GATE_T__98_I_1;
   PIN ZN0 OUT GATE_T__98_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__98_U1;
   PIN Z0 OUT T__98;
   PIN A0 IN GATE_T__98_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__99_I_2;
   PIN ZN0 OUT GATE_T__99_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__99_I_1;
   PIN ZN0 OUT GATE_T__99_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__99_U1;
   PIN Z0 OUT T__99;
   PIN A0 IN GATE_T__99_N_1;
   PIN A1 IN GATE_T__99_N_2;
 END;
 SYM INV GATE_T__100_I_2;
   PIN ZN0 OUT GATE_T__100_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__100_I_1;
   PIN ZN0 OUT GATE_T__100_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__100_U1;
   PIN Z0 OUT T__100;
   PIN A0 IN GATE_T__100_N_1;
   PIN A1 IN GATE_T__100_N_2;
 END;
 SYM INV GATE_T__101_I_1;
   PIN ZN0 OUT GATE_T__101_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__101_U1;
   PIN Z0 OUT T__101;
   PIN A0 IN GATE_T__101_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__102_I_2;
   PIN ZN0 OUT GATE_T__102_N_2;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM INV GATE_T__102_I_1;
   PIN ZN0 OUT GATE_T__102_N_1;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM AND2 GATE_T__102_U1;
   PIN Z0 OUT T__102;
   PIN A0 IN GATE_T__102_N_1;
   PIN A1 IN GATE_T__102_N_2;
 END;
 SYM INV GATE_T__103_I_1;
   PIN ZN0 OUT GATE_T__103_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__103_U1;
   PIN Z0 OUT T__103;
   PIN A0 IN GATE_T__103_N_1;
   PIN A1 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__104_I_2;
   PIN ZN0 OUT GATE_T__104_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__104_I_1;
   PIN ZN0 OUT GATE_T__104_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__104_U1;
   PIN Z0 OUT T__104;
   PIN A0 IN GATE_T__104_N_1;
   PIN A1 IN GATE_T__104_N_2;
 END;
 SYM INV GATE_T__105_I_1;
   PIN ZN0 OUT GATE_T__105_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__105_U1;
   PIN Z0 OUT T__105;
   PIN A0 IN GATE_T__105_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__106_I_1;
   PIN ZN0 OUT GATE_T__106_N_1;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM AND2 GATE_T__106_U1;
   PIN Z0 OUT T__106;
   PIN A0 IN GATE_T__106_N_1;
   PIN A1 IN IN_IR4_U1_Z0;
 END;
 SYM INV GATE_T__107_I_1;
   PIN ZN0 OUT GATE_T__107_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__107_U1;
   PIN Z0 OUT T__107;
   PIN A0 IN GATE_T__107_N_1;
   PIN A1 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__108_I_2;
   PIN ZN0 OUT GATE_T__108_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__108_I_1;
   PIN ZN0 OUT GATE_T__108_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__108_U1;
   PIN Z0 OUT T__108;
   PIN A0 IN GATE_T__108_N_1;
   PIN A1 IN GATE_T__108_N_2;
 END;
 SYM INV GATE_T__109_I_1;
   PIN ZN0 OUT GATE_T__109_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__109_U1;
   PIN Z0 OUT T__109;
   PIN A0 IN GATE_T__109_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM AND3 GATE_T__110_I_4;
   PIN Z0 OUT T__110;
   PIN A0 IN GATE_T__110_N_1;
   PIN A1 IN GATE_T__110_N_2;
   PIN A2 IN IN_IR4_U1_Z0;
 END;
 SYM INV GATE_T__110_U3;
   PIN ZN0 OUT GATE_T__110_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__110_I_2;
   PIN ZN0 OUT GATE_T__110_N_1;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM AND3 GATE_T__111_I_4;
   PIN Z0 OUT T__111;
   PIN A0 IN GATE_T__111_N_1;
   PIN A1 IN GATE_T__111_N_2;
   PIN A2 IN IN_IR7_U1_Z0;
 END;
 SYM INV GATE_T__111_U3;
   PIN ZN0 OUT GATE_T__111_N_2;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_T__111_I_2;
   PIN ZN0 OUT GATE_T__111_N_1;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM AND3 GATE_T__112_I_4;
   PIN Z0 OUT T__112;
   PIN A0 IN GATE_T__112_N_1;
   PIN A1 IN STO_Q_BLIF;
   PIN A2 IN IN_W4_U1_Z0;
 END;
 SYM INV GATE_T__112_I_2;
   PIN ZN0 OUT GATE_T__112_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM INV GATE_T__113_I_2;
   PIN ZN0 OUT GATE_T__113_N_2;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM INV GATE_T__113_I_1;
   PIN ZN0 OUT GATE_T__113_N_1;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM AND2 GATE_T__113_U1;
   PIN Z0 OUT T__113;
   PIN A0 IN GATE_T__113_N_1;
   PIN A1 IN GATE_T__113_N_2;
 END;
 SYM INV GATE_T__114_I_1;
   PIN ZN0 OUT GATE_T__114_N_1;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM AND2 GATE_T