untitled.laf

上载硬部线学校课程设计

 SYM INV GATE_T__38_U2;
   PIN ZN0 OUT GATE_T__38_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND4 GATE_T__39_U1;
   PIN Z0 OUT T__39;
   PIN A0 IN GATE_T__39_N_1;
   PIN A1 IN GATE_T__39_N_2;
   PIN A2 IN IN_IR7_U1_Z0;
   PIN A3 IN IN_IR4_U1_Z0;
 END;
 SYM INV GATE_T__39_U3;
   PIN ZN0 OUT GATE_T__39_N_2;
   PIN A0 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__39_U2;
   PIN ZN0 OUT GATE_T__39_N_1;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM AND2 GATE_T__40_U1;
   PIN Z0 OUT T__40;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN T__25;
 END;
 SYM AND2 GATE_T__41_U1;
   PIN Z0 OUT T__41;
   PIN A0 IN IN_W2_U1_Z0;
   PIN A1 IN KLD2;
 END;
 SYM AND2 GATE_T__42_U1;
   PIN Z0 OUT T__42;
   PIN A0 IN IN_W1_U1_Z0;
   PIN A1 IN KRD2;
 END;
 SYM INV GATE_T__43_I_1;
   PIN ZN0 OUT GATE_T__43_N_1;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM AND2 GATE_T__43_U1;
   PIN Z0 OUT T__43;
   PIN A0 IN GATE_T__43_N_1;
   PIN A1 IN T__26;
 END;
 SYM INV GATE_T__44_I_1;
   PIN ZN0 OUT GATE_T__44_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__44_U1;
   PIN Z0 OUT T__44;
   PIN A0 IN GATE_T__44_N_1;
   PIN A1 IN IN_SWB_U1_Z0;
 END;
 SYM AND3 GATE_T__45_I_4;
   PIN Z0 OUT T__45;
   PIN A0 IN T__76;
   PIN A1 IN T__78;
   PIN A2 IN T__77;
 END;
 SYM INV GATE_T__46_I_1;
   PIN ZN0 OUT GATE_T__46_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__46_U1;
   PIN Z0 OUT T__46;
   PIN A0 IN GATE_T__46_N_1;
   PIN A1 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__47_U1;
   PIN Z0 OUT T__47;
   PIN A0 IN IN_W3_U1_Z0;
   PIN A1 IN T__23;
 END;
 SYM AND2 GATE_T__48_U1;
   PIN Z0 OUT T__48;
   PIN A0 IN IN_W4_U1_Z0;
   PIN A1 IN STA;
 END;
 SYM AND4 GATE_T__49_U1;
   PIN Z0 OUT T__49;
   PIN A0 IN T__24;
   PIN A1 IN T__81;
   PIN A2 IN T__80;
   PIN A3 IN T__79;
 END;
 SYM AND4 GATE_T__50_U1;
   PIN Z0 OUT T__50;
   PIN A0 IN T__85;
   PIN A1 IN T__84;
   PIN A2 IN T__83;
   PIN A3 IN T__82;
 END;
 SYM AND4 GATE_T__51_U1;
   PIN Z0 OUT T__51;
   PIN A0 IN T__22;
   PIN A1 IN T__91;
   PIN A2 IN T__90;
   PIN A3 IN T__89;
 END;
 SYM AND4 GATE_T__52_U1;
   PIN Z0 OUT T__52;
   PIN A0 IN T__20;
   PIN A1 IN T__94;
   PIN A2 IN T__93;
   PIN A3 IN T__92;
 END;
 SYM INV GATE_T__53_I_2;
   PIN ZN0 OUT GATE_T__53_N_2;
   PIN A0 IN JMP;
 END;
 SYM INV GATE_T__53_I_1;
   PIN ZN0 OUT GATE_T__53_N_1;
   PIN A0 IN KRR2;
 END;
 SYM AND2 GATE_T__53_U1;
   PIN Z0 OUT T__53;
   PIN A0 IN GATE_T__53_N_1;
   PIN A1 IN GATE_T__53_N_2;
 END;
 SYM INV GATE_T__54_I_2;
   PIN ZN0 OUT GATE_T__54_N_2;
   PIN A0 IN STA;
 END;
 SYM INV GATE_T__54_I_1;
   PIN ZN0 OUT GATE_T__54_N_1;
   PIN A0 IN LDA;
 END;
 SYM AND2 GATE_T__54_U1;
   PIN Z0 OUT T__54;
   PIN A0 IN GATE_T__54_N_1;
   PIN A1 IN GATE_T__54_N_2;
 END;
 SYM INV GATE_T__55_I_1;
   PIN ZN0 OUT GATE_T__55_N_1;
   PIN A0 IN KLD2;
 END;
 SYM AND2 GATE_T__55_U1;
   PIN Z0 OUT T__55;
   PIN A0 IN GATE_T__55_N_1;
   PIN A1 IN T__15;
 END;
 SYM INV GATE_T__56_I_2;
   PIN ZN0 OUT GATE_T__56_N_2;
   PIN A0 IN IN_W1_U1_Z0;
 END;
 SYM INV GATE_T__56_I_1;
   PIN ZN0 OUT GATE_T__56_N_1;
   PIN A0 IN IN_W3_U1_Z0;
 END;
 SYM AND2 GATE_T__56_U1;
   PIN Z0 OUT T__56;
   PIN A0 IN GATE_T__56_N_1;
   PIN A1 IN GATE_T__56_N_2;
 END;
 SYM INV GATE_T__57_I_2;
   PIN ZN0 OUT GATE_T__57_N_2;
   PIN A0 IN KWE2;
 END;
 SYM INV GATE_T__57_I_1;
   PIN ZN0 OUT GATE_T__57_N_1;
   PIN A0 IN KRR2;
 END;
 SYM AND2 GATE_T__57_U1;
   PIN Z0 OUT T__57;
   PIN A0 IN GATE_T__57_N_1;
   PIN A1 IN GATE_T__57_N_2;
 END;
 SYM AND4 GATE_T__58_U1;
   PIN Z0 OUT T__58;
   PIN A0 IN T__13;
   PIN A1 IN T__101;
   PIN A2 IN T__100;
   PIN A3 IN T__99;
 END;
 SYM AND2 GATE_T__59_U1;
   PIN Z0 OUT T__59;
   PIN A0 IN IN_W3_U1_Z0;
   PIN A1 IN LDA;
 END;
 SYM AND2 GATE_T__60_U1;
   PIN Z0 OUT T__60;
   PIN A0 IN IN_W1_U1_Z0;
   PIN A1 IN KRD2;
 END;
 SYM AND4 GATE_T__61_U1;
   PIN Z0 OUT T__61;
   PIN A0 IN GATE_T__61_N_1;
   PIN A1 IN GATE_T__61_N_2;
   PIN A2 IN GATE_T__61_N_3;
   PIN A3 IN GATE_T__61_N_4;
 END;
 SYM INV GATE_T__61_I_1;
   PIN ZN0 OUT GATE_T__61_N_4;
   PIN A0 IN KLD2;
 END;
 SYM INV GATE_T__61_U4;
   PIN ZN0 OUT GATE_T__61_N_3;
   PIN A0 IN KWE2;
 END;
 SYM INV GATE_T__61_U3;
   PIN ZN0 OUT GATE_T__61_N_2;
   PIN A0 IN KRD2;
 END;
 SYM INV GATE_T__61_U2;
   PIN ZN0 OUT GATE_T__61_N_1;
   PIN A0 IN KRR2;
 END;
 SYM AND3 GATE_T__62_I_4;
   PIN Z0 OUT T__62;
   PIN A0 IN GATE_T__62_N_1;
   PIN A1 IN GATE_T__62_N_2;
   PIN A2 IN IN_SWC_U1_Z0;
 END;
 SYM INV GATE_T__62_U3;
   PIN ZN0 OUT GATE_T__62_N_2;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_T__62_I_2;
   PIN ZN0 OUT GATE_T__62_N_1;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM AND3 GATE_T__63_I_4;
   PIN Z0 OUT T__63;
   PIN A0 IN GATE_T__63_N_1;
   PIN A1 IN IN_SWA_U1_Z0;
   PIN A2 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_T__63_I_2;
   PIN ZN0 OUT GATE_T__63_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND4 GATE_T__64_U1;
   PIN Z0 OUT T__64;
   PIN A0 IN GATE_T__64_N_1;
   PIN A1 IN GATE_T__64_N_2;
   PIN A2 IN IN_W4_U1_Z0;
   PIN A3 IN T__6;
 END;
 SYM INV GATE_T__64_U3;
   PIN ZN0 OUT GATE_T__64_N_2;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM INV GATE_T__64_U2;
   PIN ZN0 OUT GATE_T__64_N_1;
   PIN A0 IN STO_Q_BLIF;
 END;
 SYM AND2 GATE_T__65_U1;
   PIN Z0 OUT T__65;
   PIN A0 IN IN_W2_U1_Z0;
   PIN A1 IN T__4;
 END;
 SYM INV GATE_T__66_I_1;
   PIN ZN0 OUT GATE_T__66_N_1;
   PIN A0 IN T__6;
 END;
 SYM AND2 GATE_T__66_U1;
   PIN Z0 OUT T__66;
   PIN A0 IN GATE_T__66_N_1;
   PIN A1 IN T__5;
 END;
 SYM AND3 GATE_T__67_I_4;
   PIN Z0 OUT T__67;
   PIN A0 IN GATE_T__67_N_1;
   PIN A1 IN IN_W1_U1_Z0;
   PIN A2 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__67_I_2;
   PIN ZN0 OUT GATE_T__67_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND3 GATE_T__68_I_4;
   PIN Z0 OUT T__68;
   PIN A0 IN GATE_T__68_N_1;
   PIN A1 IN IN_SWC_U1_Z0;
   PIN A2 IN IN_W4_U1_Z0;
 END;
 SYM INV GATE_T__68_I_2;
   PIN ZN0 OUT GATE_T__68_N_1;
   PIN A0 IN STO_Q_BLIF;
 END;
 SYM AND4 GATE_T__69_U1;
   PIN Z0 OUT T__69;
   PIN A0 IN GATE_T__69_N_1;
   PIN A1 IN GATE_T__69_N_2;
   PIN A2 IN GATE_T__69_N_3;
   PIN A3 IN GATE_T__69_N_4;
 END;
 SYM INV GATE_T__69_I_1;
   PIN ZN0 OUT GATE_T__69_N_4;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__69_U4;
   PIN ZN0 OUT GATE_T__69_N_3;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_T__69_U3;
   PIN ZN0 OUT GATE_T__69_N_2;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM INV GATE_T__69_U2;
   PIN ZN0 OUT GATE_T__69_N_1;
   PIN A0 IN STO_Q_BLIF;
 END;
 SYM AND4 GATE_T__70_U1;
   PIN Z0 OUT T__70;
   PIN A0 IN GATE_T__70_N_1;
   PIN A1 IN GATE_T__70_N_2;
   PIN A2 IN GATE_T__70_N_3;
   PIN A3 IN T__2;
 END;
 SYM INV GATE_T__70_U4;
   PIN ZN0 OUT GATE_T__70_N_3;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__70_U3;
   PIN ZN0 OUT GATE_T__70_N_2;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM INV GATE_T__70_U2;
   PIN ZN0 OUT GATE_T__70_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND3 GATE_T__71_I_4;
   PIN Z0 OUT T__71;
   PIN A0 IN T__117;
   PIN A1 IN IN_C_U1_Z0;
   PIN A2 IN T__118;
 END;
 SYM AND3 GATE_T__72_I_4;
   PIN Z0 OUT T__72;
   PIN A0 IN T__119;
   PIN A1 IN IN_W1_U1_Z0;
   PIN A2 IN T__120;
 END;
 SYM AND2 GATE_T__73_U1;
   PIN Z0 OUT T__73;
   PIN A0 IN IN_W2_U1_Z0;
   PIN A1 IN T__0;
 END;
 SYM INV GATE_T__74_I_2;
   PIN ZN0 OUT GATE_T__74_N_2;
   PIN A0 IN IN_SWA_U1_Z0;
 END;
 SYM INV GATE_T__74_I_1;
   PIN ZN0 OUT GATE_T__74_N_1;
   PIN A0 IN IN_SWB_U1_Z0;
 END;
 SYM AND2 GATE_T__74_U1;
   PIN Z0 OUT T__74;
   PIN A0 IN GATE_T__74_N_1;
   PIN A1 IN GATE_T__74_N_2;
 END;
 SYM INV GATE_T__75_I_1;
   PIN ZN0 OUT GATE_T__75_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__75_U1;
   PIN Z0 OUT T__75;
   PIN A0 IN GATE_T__75_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__76_I_1;
   PIN ZN0 OUT GATE_T__76_N_1;
   PIN A0 IN IN_IR4_U1_Z0;
 END;
 SYM AND2 GATE_T__76_U1;
   PIN Z0 OUT T__76;
   PIN A0 IN GATE_T__76_N_1;
   PIN A1 IN IN_IR5_U1_Z0;
 END;
 SYM INV GATE_T__77_I_1;
   PIN ZN0 OUT GATE_T__77_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__77_U1;
   PIN Z0 OUT T__77;
   PIN A0 IN GATE_T__77_N_1;
   PIN A1 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__78_I_1;
   PIN ZN0 OUT GATE_T__78_N_1;
   PIN A0 IN IN_SWC_U1_Z0;
 END;
 SYM AND2 GATE_T__78_U1;
   PIN Z0 OUT T__78;
   PIN A0 IN GATE_T__78_N_1;
   PIN A1 IN STO_Q_BLIF;
 END;
 SYM INV GATE_T__79_I_2;
   PIN ZN0 OUT GATE_T__79_N_2;
   PIN A0 IN IN_IR6_U1_Z0;
 END;
 SYM INV GATE_T__79_I_1;
   PIN ZN0 OUT GATE_T__79_N_1;
   PIN A0 IN IN_IR7_U1_Z0;
 END;
 SYM AND2 GATE_T__79_U1;